graphics/radeon/CP_setup.c

130 			if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) {
147 			INREG( di->regs, RADEON_RBBM_STATUS ),
148 			INREG( di->regs, RADEON_CP_STAT ),
149 			INREG( di->regs, RADEON_AIC_TLB_ADDR ),
150 			INREG( di->regs, RADEON_AIC_TLB_DATA ));
167 			int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
186 	OUTREGP( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL,
192 		if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT )
208 	vuint8 *regs = di->regs;
217 	clock_cntl_index = INREG( regs, RADEON_CLOCK_CNTL_INDEX );
218 	RADEONPllErrataAfterIndex( regs, di->asic );	// drm has no errata here!
219 	mclk_cntl = Radeon_INPLL( regs, di->asic, RADEON_MCLK_CNTL );
222 	Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl |
231     host_path_cntl = INREG( regs, RADEON_HOST_PATH_CNTL );
232 	rbbm_soft_reset = INREG( regs, RADEON_RBBM_SOFT_RESET );
234 	OUTREG( regs, RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
242 	INREG( regs, RADEON_RBBM_SOFT_RESET);
243 	OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset &
251 	INREG( regs, RADEON_RBBM_SOFT_RESET);
253     OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET );
254     INREG( regs, RADEON_HOST_PATH_CNTL );
255     OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl );
257 	Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl );
258    	OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
259    	//RADEONPllErrataAfterIndex( regs, di->asic ); // drm doesn't do this here!
260    	OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
265 		cur_read_ptr = INREG( regs, RADEON_CP_RB_RPTR );
266 		OUTREG( regs, RADEON_CP_RB_WPTR, cur_read_ptr );
312 	OUTREG( di->regs, RADEON_CP_ME_RAM_ADDR, 0 );
315 		OUTREG( di->regs, RADEON_CP_ME_RAM_DATAH, microcode[i][1] );
316 		OUTREG( di->regs, RADEON_CP_ME_RAM_DATAL, microcode[i][0] );
326 	vuint8 *regs = di->regs;
351 	OUTREG( regs, RADEON_CP_RB_BASE, cp->ring.vm_base );
356 	OUTREG( regs, RADEON_CP_RB_CNTL, radeon_log2( cp->ring.size / 2 ));
362 	OUTREG( regs, RADEON_CP_RB_WPTR_DELAY, 0 );
367 	OUTREG( regs, RADEON_CP_RB_RPTR, 0 );
368 	OUTREG( regs, RADEON_CP_RB_WPTR, 0 );
377 	vuint8 *regs = di->regs;
383 	OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
385 	INREG( regs, RADEON_CP_CSQ_CNTL );
393 	vuint8 *regs = di->regs;
415 	OUTREG( regs, RADEON_CP_RB_RPTR_ADDR, cp->feedback.head_vm_address );
422 	OUTREG( regs, RADEON_SCRATCH_ADDR, cp->feedback.scratch_vm_start );
423 	OUTREG( regs, RADEON_SCRATCH_UMSK, 0x3f );
434 	vuint8 *regs = di->regs;
437 	OUTREG( regs, RADEON_SCRATCH_UMSK, 0x0 );
521 	OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
522 	INREG( di->regs, RADEON_CP_CSQ_CNTL );
545 		OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM );
548 		OUTREGP( di->regs, RADEON_BUS_CNTL, 0, ~RADEON_BUS_MASTER_DIS );
555 	OUTREG( di->regs, RADEON_ISYNC_CNTL,
561 	SHOW_FLOW( 3, "bus_cntl=%" B_PRIx32, INREG( di->regs, RADEON_BUS_CNTL ));
582 	vuint8 *regs = di->regs;
588 	OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
590 	INREG( regs, RADEON_CP_CSQ_CNTL );
642     vuint8 *regs = di->regs;
649 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
657 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
660 			tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
664 			Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);
666 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
675 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
677 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
679 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);
681 			tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
687 			Radeon_OUTPLL(regs, asic, RADEON_MCLK_CNTL, tmp);
689 			tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
693 			Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);
695 			tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
710 			Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
712 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
736 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
741 				tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
745 				Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);
750 				tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
753 				Radeon_OUTPLL(regs, asic, RADEON_MCLK_CNTL, tmp);
760 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
762 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);
766 			tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
775 			Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
778 			tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
781 			Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);
787 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
788 			if ((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) > RADEON_CFG_ATI_REV_A13) {
796 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
801 				tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
808 				Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);
810 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
820 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
822 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
825 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);
827 				tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
830 				Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);
832 				tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
846 				Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
848 				tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_MISC);
851 				Radeon_OUTPLL(regs, asic, RADEON_MCLK_MISC, tmp);
853 				tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
868 					tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
870 						if (INREG( regs, RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
880 				Radeon_OUTPLL(regs, asic, RADEON_MCLK_CNTL, tmp);
882 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
885 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
888 				tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
892 				Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);
895 			tmp = Radeon_INPLL(regs, asic, RADEON_CLK_PWRMGT_CNTL);
903 			Radeon_OUTPLL(regs, asic, RADEON_CLK_PWRMGT_CNTL, tmp);
906 			tmp = Radeon_INPLL(regs, asic, RADEON_CLK_PIN_CNTL);
908 			Radeon_OUTPLL(regs, asic, RADEON_CLK_PIN_CNTL, tmp);
914 			tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
920 				((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
923 				((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <=
930 			Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);
935 				tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
941 					((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
946 				Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);
953 				((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
956 				tmp = Radeon_INPLL(regs, asic, RADEON_PLL_PWRMGT_CNTL);
958 				Radeon_OUTPLL(regs, asic, RADEON_PLL_PWRMGT_CNTL, tmp);
963 			tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
972 			Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
975 			tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
979 			Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);