graphics/radeon/CP_setup.c

83 		mem_type = di->si->nonlocal_type; \
84 	res = mem_alloc( di->memmgr[mem_type], asize, NULL, handle, offset );
89 	((uint8 *)(memory_type == mt_local ? di->si->local_mem : \
90 	(memory_type == mt_PCI ? di->pci_gart.buffer.ptr : di->agp_gart.buffer.ptr)) \
96 	(di->si->memory[(memory_type)].virtual_addr_start + (offset))
102 		di->memmgr[ mem_type == mt_nonlocal ? di->si->nonlocal_type : mem_type], \
108 void Radeon_DiscardAllIndirectBuffers( device_info *di );
113 void Radeon_FlushPixelCache( device_info *di );
119 void Radeon_WaitForIdle( device_info *di, bool acquire_lock, bool keep_lock )
122 		ACQUIRE_BEN( di->si->cp.lock );
124 	Radeon_WaitForFifo( di, 64 );
130 			if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) {
131 				Radeon_FlushPixelCache( di );
134 					RELEASE_BEN( di->si->cp.lock );
147 			INREG( di->regs, RADEON_RBBM_STATUS ),
148 			INREG( di->regs, RADEON_CP_STAT ),
149 			INREG( di->regs, RADEON_AIC_TLB_ADDR ),
150 			INREG( di->regs, RADEON_AIC_TLB_DATA ));
152 		LOG( di->si->log, _Radeon_WaitForIdle );
154 		Radeon_ResetEngine( di );
161 void Radeon_WaitForFifo( device_info *di, int entries )
167 			int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
175 		LOG( di->si->log, _Radeon_WaitForFifo );
177 		Radeon_ResetEngine( di );
182 void Radeon_FlushPixelCache( device_info *di )
186 	OUTREGP( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL,
192 		if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT )
199 	LOG( di->si->log, _Radeon_FlushPixelCache );
206 void Radeon_ResetEngine( device_info *di )
208 	vuint8 *regs = di->regs;
209 	shared_info *si = di->si;
215 	Radeon_FlushPixelCache( di );
218 	RADEONPllErrataAfterIndex( regs, di->asic );	// drm has no errata here!
219 	mclk_cntl = Radeon_INPLL( regs, di->asic, RADEON_MCLK_CNTL );
222 	Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl |
257 	Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl );
259    	//RADEONPllErrataAfterIndex( regs, di->asic ); // drm doesn't do this here!
262 	if ( di->acc_dma )
278 		Radeon_DiscardAllIndirectBuffers( di );
287 static void loadMicroEngineRAMData( device_info *di )
294 	switch( di->asic ) {
310 	Radeon_WaitForIdle( di, false, false );
312 	OUTREG( di->regs, RADEON_CP_ME_RAM_ADDR, 0 );
315 		OUTREG( di->regs, RADEON_CP_ME_RAM_DATAH, microcode[i][1] );
316 		OUTREG( di->regs, RADEON_CP_ME_RAM_DATAL, microcode[i][0] );
321 static status_t initRingBuffer( device_info *di, int aring_size )
324 	shared_info *si = di->si;
326 	vuint8 *regs = di->regs;
375 static void uninitRingBuffer( device_info *di )
377 	vuint8 *regs = di->regs;
380 	Radeon_ResetEngine( di );
387 	FREE_MEM( mt_nonlocal, di->si->cp.ring.mem_handle );
390 static status_t initCPFeedback( device_info *di )
392 	CP_info *cp = &di->si->cp;
393 	vuint8 *regs = di->regs;
432 static void uninitCPFeedback( device_info *di )
434 	vuint8 *regs = di->regs;
439 	FREE_MEM( mt_PCI, di->si->cp.feedback.mem_handle );
442 static status_t initIndirectBuffers( device_info *di )
444 	CP_info *cp = &di->si->cp;
482 static void uninitIndirectBuffers( device_info *di )
484 	FREE_MEM( mt_nonlocal, di->si->cp.buffers.mem_handle );
488 status_t Radeon_InitCP( device_info *di )
498 	memset( &di->si->cp, 0, sizeof( di->si->cp ));
500 	if( (res = INIT_BEN( di->si->cp.lock, "Radeon CP" )) < 0 )
510     set_sem_owner( di->si->cp.lock.sem, thinfo.team );
513 	if ( di->acc_dma ) loadMicroEngineRAMData( di );
516 	Radeon_ResetEngine( di );
521 	OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
522 	INREG( di->regs, RADEON_CP_CSQ_CNTL );
525 	Radeon_ResetEngine( di );
527 	if ( di->acc_dma )
529 		res = initRingBuffer( di, CP_RING_SIZE );
533 		res = initCPFeedback( di );
537 		res = initIndirectBuffers( di );
542 		Radeon_WaitForIdle( di, false, false );
545 		OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM );
548 		OUTREGP( di->regs, RADEON_BUS_CNTL, 0, ~RADEON_BUS_MASTER_DIS );
555 	OUTREG( di->regs, RADEON_ISYNC_CNTL,
561 	SHOW_FLOW( 3, "bus_cntl=%" B_PRIx32, INREG( di->regs, RADEON_BUS_CNTL ));
570 	uninitCPFeedback( di );
572 	uninitRingBuffer( di );
574 	DELETE_BEN( di->si->cp.lock );
580 void Radeon_UninitCP( device_info *di )
582 	vuint8 *regs = di->regs;
585 	Radeon_ResetEngine( di );
592 	if ( di->acc_dma )
594 		uninitRingBuffer( di );
595 		uninitCPFeedback( di );
596 		uninitIndirectBuffers( di );
599 	DELETE_BEN( di->si->cp.lock );
606 void Radeon_DiscardAllIndirectBuffers( device_info *di )
608 	CP_info *cp = &di->si->cp;
640 void Radeon_SetDynamicClock( device_info *di, int mode)
642     vuint8 *regs = di->regs;
643     radeon_type asic = di->asic;
648 		if ( di->num_crtc != 2 ) {
716 			if ( di->num_crtc != 2 ) {
749 			if (di->is_igp) {
786 		if ( di->num_crtc != 2 ) {
869 					if (di->ram.width == 64) {