graphics/radeon/CP_setup.c

122 		ACQUIRE_BEN( di->si->cp.lock );
134 					RELEASE_BEN( di->si->cp.lock );
268 		//if( si->cp.ring.head ) {
270 		if( si->cp.feedback.mem_handle != 0 ) {
271 			*(uint32 *)MEM2CPU( si->cp.feedback.mem_type, si->cp.feedback.head_mem_offset) =
273 			//	*si->cp.ring.head = cur_read_ptr;
274 			si->cp.ring.tail = cur_read_ptr;
325 	CP_info *cp = &si->cp;
330 	memset( &cp->ring, 0, sizeof( cp->ring ));
338 		&cp->ring.mem_handle, &offset );
346 	cp->ring.mem_type = memory_type;
347 	cp->ring.mem_offset = offset;
348 	cp->ring.vm_base = MEM2GC( memory_type, offset );
349 	cp->ring.size = aring_size;
350 	cp->ring.tail_mask = aring_size - 1;
351 	OUTREG( regs, RADEON_CP_RB_BASE, cp->ring.vm_base );
352 	SHOW_INFO( 3, "CP buffer address=%" B_PRIx32, cp->ring.vm_base );
356 	OUTREG( regs, RADEON_CP_RB_CNTL, radeon_log2( cp->ring.size / 2 ));
357 	SHOW_INFO( 3, "CP buffer size mask=%d", radeon_log2( cp->ring.size / 2 ) );
364 	memset( MEM2CPU( cp->ring.mem_type, cp->ring.mem_offset), 0, cp->ring.size * 4 );
369 	//*cp->ring.head = 0;
370 	cp->ring.tail = 0;
387 	FREE_MEM( mt_nonlocal, di->si->cp.ring.mem_handle );
392 	CP_info *cp = &di->si->cp;
404 		&cp->feedback.mem_handle, &offset );
412 	cp->feedback.mem_type = memory_type;
413 	cp->feedback.head_mem_offset = offset;
414 	cp->feedback.head_vm_address = MEM2GC( memory_type, cp->feedback.head_mem_offset );
415 	OUTREG( regs, RADEON_CP_RB_RPTR_ADDR, cp->feedback.head_vm_address );
417 		cp->feedback.head_vm_address );
420 	cp->feedback.scratch_mem_offset = offset + RADEON_SCRATCH_REG_OFFSET;
421 	cp->feedback.scratch_vm_start = MEM2GC( memory_type, cp->feedback.scratch_mem_offset );
422 	OUTREG( regs, RADEON_SCRATCH_ADDR, cp->feedback.scratch_vm_start );
425 	*(uint32 *)MEM2CPU( cp->feedback.mem_type, cp->feedback.head_mem_offset) = 0;
426 	memset( MEM2CPU( cp->feedback.mem_type, cp->feedback.scratch_mem_offset), 0, 0x40 );
427 	//*cp->ring.head = 0;
439 	FREE_MEM( mt_PCI, di->si->cp.feedback.mem_handle );
444 	CP_info *cp = &di->si->cp;
453 		true, &cp->buffers.mem_handle, &offset );
460 	cp->buffers.mem_type = memory_type;
461 	cp->buffers.mem_offset = offset;
462 	cp->buffers.vm_start = MEM2GC( memory_type, cp->buffers.mem_offset );
465 		cp->buffers.buffers[i].next = i + 1;
468 	cp->buffers.buffers[i].next = -1;
470 	cp->buffers.free_list = 0;
471 	cp->buffers.oldest = -1;
472 	cp->buffers.newest = -1;
473 	cp->buffers.active_state = -1;
474 	cp->buffers.cur_tag = 0;
476 	memset( MEM2CPU( cp->buffers.mem_type, cp->buffers.mem_offset), 0,
484 	FREE_MEM( mt_nonlocal, di->si->cp.buffers.mem_handle );
498 	memset( &di->si->cp, 0, sizeof( di->si->cp ));
500 	if( (res = INIT_BEN( di->si->cp.lock, "Radeon CP" )) < 0 )
510     set_sem_owner( di->si->cp.lock.sem, thinfo.team );
574 	DELETE_BEN( di->si->cp.lock );
599 	DELETE_BEN( di->si->cp.lock );
608 	CP_info *cp = &di->si->cp;
611 	if( cp->buffers.mem_handle == 0 )
615 	while( cp->buffers.oldest != -1 ) {
617 			&cp->buffers.buffers[cp->buffers.oldest];
620 		SHOW_FLOW( 0, "%d", cp->buffers.oldest );
626 			cp->buffers.newest = -1;
629 		oldest_buffer->next = cp->buffers.free_list;
630 		cp->buffers.free_list = cp->buffers.oldest;
632 		cp->buffers.oldest = tmp_oldest_buffer;