Lines Matching refs:REGISTER_BLOCK
669 blocks[REGISTER_BLOCK(REGS_FLAT)] = 0;
674 blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)]
676 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)]
678 blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)]
680 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)]
682 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)]
686 blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)]
688 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)]
690 blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)]
692 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)]
694 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)]
701 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] += VLV_DISPLAY_BASE;
702 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] += VLV_DISPLAY_BASE;
706 blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)]);
708 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)]);
710 blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)]);
712 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)]);
714 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)]);