audio/ac97/ac97.c

43 bool ac97_reg_is_valid(ac97_dev *dev, uint8 reg);
44 void ac97_amp_enable(ac97_dev *dev, bool onoff);
45 void ac97_dump_capabilities(ac97_dev *dev);
46 void ac97_detect_capabilities(ac97_dev *dev);
47 void ac97_detect_rates(ac97_dev *dev);
48 void ac97_update_register_cache(ac97_dev *dev);
88 static void default_init(ac97_dev *dev);
89 static void ad1819_init(ac97_dev *dev);
90 static void ad1881_init(ac97_dev *dev);
91 static void ad1885_init(ac97_dev *dev);
92 static void ad1886_init(ac97_dev *dev);
93 static void ad1980_init(ac97_dev *dev);
94 static void ad1981b_init(ac97_dev *dev);
95 static void alc203_init(ac97_dev *dev);
96 static void alc650_init(ac97_dev *dev);
97 static void alc655_init(ac97_dev *dev);
98 static void alc850_init(ac97_dev *dev);
99 static void stac9708_init(ac97_dev *dev);
100 static void stac9721_init(ac97_dev *dev);
101 static void stac9744_init(ac97_dev *dev);
102 static void stac9756_init(ac97_dev *dev);
103 static void stac9758_init(ac97_dev *dev);
104 static void tr28028_init(ac97_dev *dev);
105 static void wm9701_init(ac97_dev *dev);
106 static void wm9703_init(ac97_dev *dev);
107 static void wm9704_init(ac97_dev *dev);
109 bool ad1819_set_rate(ac97_dev *dev, uint8 reg, uint32 rate);
110 bool ad1819_get_rate(ac97_dev *dev, uint8 reg, uint32 *rate);
243 	ac97_dev *dev;
247 	*_dev = dev = (ac97_dev *) malloc(sizeof(ac97_dev));
248 	memset(dev->reg_cache, 0, sizeof(dev->reg_cache));
249 	dev->cookie = cookie;
250 	dev->reg_read = reg_read;
251 	dev->reg_write = reg_write;
252 	dev->set_rate = 0;
253 	dev->get_rate = 0;
254 	dev->clock = 48000; /* default clock on non-broken motherboards */
255 	dev->min_vsr = 0x0001;
256 	dev->max_vsr = 0xffff;
257 	dev->reversed_eamp_polarity = false;
258 	dev->capabilities = 0;
260 	dev->subsystem = (subvendor_id << 16) | subsystem_id;
262 	if (dev->subsystem == 0x161f202f
263 		|| dev->subsystem == 0x161f203a
264 		|| dev->subsystem == 0x161f203e
265 		|| dev->subsystem == 0x161f204c
266 		|| dev->subsystem == 0x104d8144
267 		|| dev->subsystem == 0x104d8197
268 		|| dev->subsystem == 0x104d81c0
269 		|| dev->subsystem == 0x104d81c5
270 		|| dev->subsystem == 0x103c3089
271 		|| dev->subsystem == 0x103c309a
272 		|| dev->subsystem == 0x10338213
273 		|| dev->subsystem == 0x103382be) {
274 		dev->reversed_eamp_polarity = true;
279 	ac97_reg_uncached_write(dev, AC97_RESET, 0x0000);
281 		if ((ac97_reg_uncached_read(dev, AC97_POWERDOWN) & 0xf) == 0xf)
286 	dev->codec_id = ((uint32)reg_read(cookie, AC97_VENDOR_ID1) << 16) | reg_read(cookie, AC97_VENDOR_ID2);
287 	codec = find_codec_table(dev->codec_id);
288 	dev->codec_info = codec->info;
289 	dev->init = codec->init;
291 	dev->codec_3d_stereo_enhancement = stereo_enhancement_technique[(ac97_reg_cached_read(dev, AC97_RESET) >> 10) & 31];
294 	ac97_update_register_cache(dev);
296 	ac97_reg_update_bits(dev, AC97_EXTENDED_STAT_CTRL, 1, 1); // enable variable rate audio
298 	ac97_detect_capabilities(dev);
300 	dev->init(dev);
301 	ac97_amp_enable(dev, true);
304 	ac97_reg_update(dev, AC97_CENTER_LFE_VOLUME, 0x0000);	/* set LFE & center volume 0dB */
305 	ac97_reg_update(dev, AC97_SURR_VOLUME, 0x0000);			/* set surround volume 0dB */
306 	ac97_reg_update(dev, AC97_MASTER_VOLUME, 0x0000);		/* set master output 0dB */
307 	ac97_reg_update(dev, AC97_AUX_OUT_VOLUME, 0x0000);		/* set aux output 0dB */
308 	ac97_reg_update(dev, AC97_MONO_VOLUME, 0x0000);			/* set mono output 0dB */
309 	ac97_reg_update(dev, AC97_PCM_OUT_VOLUME, 0x0808);		/* enable pcm-out */
310 	ac97_reg_update(dev, AC97_CD_VOLUME, 0x0808);			/* enable cd-in */
311 	ac97_reg_update(dev, AC97_LINE_IN_VOLUME, 0x0808);		/* enable line-in */
314 	ac97_reg_update(dev, AC97_RECORD_SELECT, 0x0404);
316 	LOG(("codec vendor id      = %#08" B_PRIx32 "\n", dev->codec_id));
317 	LOG(("codec description     = %s\n", dev->codec_info));
318 	LOG(("codec 3d enhancement = %s\n", dev->codec_3d_stereo_enhancement));
320 	ac97_dump_capabilities(dev);
325 ac97_detach(ac97_dev *dev)
328 	ac97_reg_update_bits(dev, AC97_CENTER_LFE_VOLUME, 0x8000, 0x8000);
329 	ac97_reg_update_bits(dev, AC97_SURR_VOLUME, 0x8000, 0x8000);
330 	ac97_reg_update_bits(dev, AC97_MASTER_VOLUME, 0x8000, 0x8000);
331 	ac97_reg_update_bits(dev, AC97_AUX_OUT_VOLUME, 0x8000, 0x8000);
332 	ac97_reg_update_bits(dev, AC97_MONO_VOLUME, 0x8000, 0x8000);
333 	ac97_reg_update_bits(dev, AC97_PCM_OUT_VOLUME, 0x8000, 0x8000);
334 	ac97_reg_update_bits(dev, AC97_CD_VOLUME, 0x8000, 0x8000);
335 	ac97_reg_update_bits(dev, AC97_LINE_IN_VOLUME, 0x8000, 0x8000);
337 	ac97_amp_enable(dev, false);
339 	free(dev);
344 ac97_suspend(ac97_dev *dev)
346 	ac97_amp_enable(dev, false);
351 ac97_resume(ac97_dev *dev)
353 	ac97_amp_enable(dev, true);
358 ac97_reg_cached_write(ac97_dev *dev, uint8 reg, uint16 value)
360 	if (!ac97_reg_is_valid(dev, reg))
362 	dev->reg_write(dev->cookie, reg, value);
363 	dev->reg_cache[reg] = value;
368 ac97_reg_cached_read(ac97_dev *dev, uint8 reg)
370 	if (!ac97_reg_is_valid(dev, reg))
372 	return dev->reg_cache[reg];
376 ac97_reg_uncached_write(ac97_dev *dev, uint8 reg, uint16 value)
378 	if (!ac97_reg_is_valid(dev, reg))
380 	dev->reg_write(dev->cookie, reg, value);
385 ac97_reg_uncached_read(ac97_dev *dev, uint8 reg)
387 	if (!ac97_reg_is_valid(dev, reg))
389 	return dev->reg_read(dev->cookie, reg);
394 ac97_reg_update(ac97_dev *dev, uint8 reg, uint16 value)
396 	if (!ac97_reg_is_valid(dev, reg))
398 	if (ac97_reg_cached_read(dev, reg) == value)
400 	ac97_reg_cached_write(dev, reg, value);
406 ac97_reg_update_bits(ac97_dev *dev, uint8 reg, uint16 mask, uint16 value)
409 	if (!ac97_reg_is_valid(dev, reg))
411 	old = ac97_reg_cached_read(dev, reg);
416 	ac97_reg_cached_write(dev, reg, value);
422 ac97_update_register_cache(ac97_dev *dev)
426 		dev->reg_cache[reg] = ac97_reg_uncached_read(dev, reg);
431 ac97_set_rate(ac97_dev *dev, uint8 reg, uint32 rate)
436 	if (dev->set_rate)
437 		return dev->set_rate(dev, reg, rate);
439 	value = (uint32)((rate * 48000ULL) / dev->clock); /* need 64 bit calculation for rates 96000 or higher */
444 		dev->clock, rate, value));
447 	if (ac97_reg_cached_read(dev, AC97_EXTENDED_STAT_CTRL) & 0x0002)
450 	if (value < dev->min_vsr || value > dev->max_vsr)
453 	old = ac97_reg_cached_read(dev, reg);
454 	ac97_reg_cached_write(dev, reg, value);
455 	if (value != ac97_reg_uncached_read(dev, reg)) {
456 		LOG(("ac97_set_rate failed, new rate %d\n", ac97_reg_uncached_read(dev, reg)));
457 		ac97_reg_cached_write(dev, reg, old);
466 ac97_get_rate(ac97_dev *dev, uint8 reg, uint32 *rate)
470 	if (dev->get_rate)
471 		return dev->get_rate(dev, reg, rate);
473 	value = ac97_reg_cached_read(dev, reg);
478 	if (ac97_reg_cached_read(dev, AC97_EXTENDED_STAT_CTRL) & 0x0002)
481 	*rate = (uint32)((value * (uint64)dev->clock) / 48000); /* need 64 bit calculation to avoid overflow*/
487 ac97_set_clock(ac97_dev *dev, uint32 clock)
490 	dev->clock = clock;
491 	ac97_detect_rates(dev);
492 	ac97_dump_capabilities(dev);
497 ac97_detect_capabilities(ac97_dev *dev)
501 	val = ac97_reg_cached_read(dev, AC97_RESET);
503 		dev->capabilities |= CAP_PCM_MIC;
505 		dev->capabilities |= CAP_BASS_TREBLE_CTRL;
507 		dev->capabilities |= CAP_SIMULATED_STEREO;
509 		dev->capabilities |= CAP_HEADPHONE_OUT;
511 		dev->capabilities |= CAP_LAUDNESS;
513 		dev->capabilities |= CAP_DAC_18BIT;
515 		dev->capabilities |= CAP_DAC_20BIT;
517 		dev->capabilities |= CAP_ADC_18BIT;
519 		dev->capabilities |= CAP_ADC_20BIT;
521 		dev->capabilities |= CAP_3D_ENHANCEMENT;
523 	val = ac97_reg_cached_read(dev, AC97_EXTENDED_ID);
525 		dev->capabilities |= CAP_VARIABLE_PCM;
527 		dev->capabilities |= CAP_DOUBLE_PCM;
529 		dev->capabilities |= CAP_SPDIF;
531 		dev->capabilities |= CAP_VARIABLE_MIC;
533 		dev->capabilities |= CAP_CENTER_DAC;
535 		dev->capabilities |= CAP_SURR_DAC;
537 		dev->capabilities |= CAP_LFE_DAC;
539 		dev->capabilities |= CAP_AMAP;
541 		dev->capabilities |= CAP_REV21;
543 		dev->capabilities |= CAP_REV22;
545 		dev->capabilities |= CAP_REV23;
547 	ac97_detect_rates(dev);
551 ac97_detect_rates(ac97_dev *dev)
555 	dev->capabilities &= ~CAP_PCM_RATE_MASK;
557 	if (!ac97_get_rate(dev, AC97_PCM_FRONT_DAC_RATE, &oldrate))
560 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 20000))
561 		dev->capabilities |= CAP_PCM_RATE_CONTINUOUS;
562 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 8000))
563 		dev->capabilities |= CAP_PCM_RATE_8000;
564 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 11025))
565 		dev->capabilities |= CAP_PCM_RATE_11025;
566 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 12000))
567 		dev->capabilities |= CAP_PCM_RATE_12000;
568 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 16000))
569 		dev->capabilities |= CAP_PCM_RATE_16000;
570 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 22050))
571 		dev->capabilities |= CAP_PCM_RATE_22050;
572 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 24000))
573 		dev->capabilities |= CAP_PCM_RATE_24000;
574 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 32000))
575 		dev->capabilities |= CAP_PCM_RATE_32000;
576 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 44100))
577 		dev->capabilities |= CAP_PCM_RATE_44100;
578 	if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 48000))
579 		dev->capabilities |= CAP_PCM_RATE_48000;
581 	if (dev->capabilities & CAP_DOUBLE_PCM) {
583 		if (ac97_reg_update_bits(dev, AC97_EXTENDED_STAT_CTRL, 0x0002, 0x0002)) {
584 			if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 88200))
585 				dev->capabilities |= CAP_PCM_RATE_88200;
586 			if (ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 96000))
587 				dev->capabilities |= CAP_PCM_RATE_96000;
589 			ac97_reg_update_bits(dev, AC97_EXTENDED_STAT_CTRL, 0x0002, 0x0000);
593 	ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, oldrate);
598 ac97_dump_capabilities(ac97_dev *dev)
601 	if (ac97_has_capability(dev, CAP_PCM_MIC))
603 	if (ac97_has_capability(dev, CAP_BASS_TREBLE_CTRL))
605 	if (ac97_has_capability(dev, CAP_SIMULATED_STEREO))
607 	if (ac97_has_capability(dev, CAP_HEADPHONE_OUT))
609 	if (ac97_has_capability(dev, CAP_LAUDNESS))
611 	if (ac97_has_capability(dev, CAP_DAC_18BIT))
613 	if (ac97_has_capability(dev, CAP_DAC_20BIT))
615 	if (ac97_has_capability(dev, CAP_ADC_18BIT))
617 	if (ac97_has_capability(dev, CAP_ADC_20BIT))
619 	if (ac97_has_capability(dev, CAP_3D_ENHANCEMENT))
621 	if (ac97_has_capability(dev, CAP_VARIABLE_PCM))
623 	if (ac97_has_capability(dev, CAP_DOUBLE_PCM))
625 	if (ac97_has_capability(dev, CAP_VARIABLE_MIC))
627 	if (ac97_has_capability(dev, CAP_CENTER_DAC))
629 	if (ac97_has_capability(dev, CAP_SURR_DAC))
631 	if (ac97_has_capability(dev, CAP_LFE_DAC))
633 	if (ac97_has_capability(dev, CAP_AMAP))
635 	if (ac97_has_capability(dev, CAP_REV21))
637 	if (ac97_has_capability(dev, CAP_REV22))
639 	if (ac97_has_capability(dev, CAP_REV23))
641 	if (ac97_has_capability(dev, CAP_PCM_RATE_CONTINUOUS))
643 	if (ac97_has_capability(dev, CAP_PCM_RATE_8000))
645 	if (ac97_has_capability(dev, CAP_PCM_RATE_11025))
647 	if (ac97_has_capability(dev, CAP_PCM_RATE_12000))
649 	if (ac97_has_capability(dev, CAP_PCM_RATE_16000))
651 	if (ac97_has_capability(dev, CAP_PCM_RATE_22050))
653 	if (ac97_has_capability(dev, CAP_PCM_RATE_24000))
655 	if (ac97_has_capability(dev, CAP_PCM_RATE_32000))
657 	if (ac97_has_capability(dev, CAP_PCM_RATE_44100))
659 	if (ac97_has_capability(dev, CAP_PCM_RATE_48000))
661 	if (ac97_has_capability(dev, CAP_PCM_RATE_88200))
663 	if (ac97_has_capability(dev, CAP_PCM_RATE_96000))
669 ac97_has_capability(ac97_dev *dev, uint64 cap)
671 	// return (dev->capabilities & cap); // does not work because of 64 bit to integer trucation
672 	return (dev->capabilities & cap) != 0;
680 ac97_reg_is_valid(ac97_dev *dev, uint8 reg)
687 	switch (dev->codec_id) {
727 ac97_amp_enable(ac97_dev *dev, bool yesno)
729 	switch (dev->codec_id) {
735 				ac97_reg_cached_write(dev, 0x68, 0x8004);
737 				ac97_reg_cached_write(dev, 0x68, 0);
741 			LOG(("ac97_amp_enable, reverse eamp = %d\n", dev->reversed_eamp_polarity));
742 			LOG(("powerdown register was = %#04x\n", ac97_reg_uncached_read(dev, AC97_POWERDOWN)));
743 			if (dev->reversed_eamp_polarity)
746 				ac97_reg_cached_write(dev, AC97_POWERDOWN, ac97_reg_uncached_read(dev, AC97_POWERDOWN) & ~0x8000); /* switch on (low active) */
748 				ac97_reg_cached_write(dev, AC97_POWERDOWN, ac97_reg_uncached_read(dev, AC97_POWERDOWN) | 0x8000); /* switch off */
749 			LOG(("powerdown register is = %#04x\n", ac97_reg_uncached_read(dev, AC97_POWERDOWN)));
756 ad1819_set_rate(ac97_dev *dev, uint8 reg, uint32 rate)
760 	value = (uint32)((rate * 48000ULL) / dev->clock); /* need 64 bit calculation for rates 96000 or higher */
765 		dev->clock, rate, value));
772 			ac97_reg_cached_write(dev, AC97_AD_SAMPLE_RATE_0, value);
776 			ac97_reg_cached_write(dev, AC97_AD_SAMPLE_RATE_1, value);
786 ad1819_get_rate(ac97_dev *dev, uint8 reg, uint32 *rate)
792 			value = ac97_reg_cached_read(dev, AC97_AD_SAMPLE_RATE_0);
796 			value = ac97_reg_cached_read(dev, AC97_AD_SAMPLE_RATE_1);
803 	*rate = (uint32)((value * (uint64)dev->clock) / 48000); /* need 64 bit calculation to avoid overflow*/
809 default_init(ac97_dev *dev)
816 ad1819_init(ac97_dev *dev)
821 	ac97_reg_cached_write(dev, AC97_AD_SERIAL_CONFIG, 0x7000);
822 	ac97_update_register_cache(dev);
829 	ac97_reg_cached_write(dev, AC97_AD_MISC_CONTROL, 0x0101);
831 	dev->set_rate = ad1819_set_rate;
832 	dev->get_rate = ad1819_get_rate;
833 	ac97_detect_rates(dev);
834 	ac97_set_rate(dev, AC97_PCM_FRONT_DAC_RATE, 48000);
835 	ac97_set_rate(dev, AC97_PCM_L_R_ADC_RATE, 48000);
840 ad1881_init(ac97_dev *dev)
846 	ac97_reg_cached_write(dev, AC97_AD_SERIAL_CONFIG, 0x7000);
847 	ac97_update_register_cache(dev);
850 	ac97_reg_cached_write(dev, AC97_AD_MISC_CONTROL, 0x0404);
853 	dev->min_vsr = 0x1B58;	/*  7kHz */
854 	dev->max_vsr = 0xBB80;	/* 48kHz */
859 ad1885_init(ac97_dev *dev)
862 	ad1881_init(dev);
865 	ac97_reg_cached_write(dev, AC97_AD_JACK_SENSE, ac97_reg_cached_read(dev, AC97_AD_JACK_SENSE) | 0x0300);
870 ad1886_init(ac97_dev *dev)
873 	ad1881_init(dev);
876 	ac97_reg_cached_write(dev, AC97_AD_JACK_SENSE, 0x0010);
878 	ac97_reg_cached_write(dev, AC97_SPDIF_CONTROL, 0x2a20);
883 ad1980_init(ac97_dev *dev)
890 	ac97_reg_cached_write(dev, AC97_AD_SERIAL_CONFIG, 0x1001);
891 	ac97_update_register_cache(dev);
898 	ac97_reg_cached_write(dev, AC97_AD_MISC_CONTROL, 0x0400);
903 ad1981b_init(ac97_dev *dev)
906 	if (dev->subsystem == 0x0e11005a
907 		|| dev->subsystem == 0x103c006d
908 		|| dev->subsystem == 0x103c088c
909 		|| dev->subsystem == 0x103c0890
910 		|| dev->subsystem == 0x103c0934
911 		|| dev->subsystem == 0x103c0938
912 		|| dev->subsystem == 0x103c0944
913 		|| dev->subsystem == 0x103c099c
914 		|| dev->subsystem == 0x101402d9) {
915 		ac97_reg_cached_write(dev, AC97_AD_JACK_SENSE,
916 				ac97_reg_cached_read(dev, AC97_AD_JACK_SENSE) | 0x0800);
922 alc203_init(ac97_dev *dev)
926 	ac97_reg_update_bits(dev, AC97_ALC650_CLOCK_SOURCE, 0x400, 0x400);
931 alc650_init(ac97_dev *dev)
938 	ac97_reg_cached_write(dev, AC97_ALC650_MULTI_CHAN_CTRL, 0x0007);
944 	ac97_reg_cached_write(dev, AC97_ALC650_SURR_VOLUME, 0x0808);
945 	ac97_reg_cached_write(dev, AC97_ALC650_CEN_LFE_VOLUME, 0x0808);
950 alc655_init(ac97_dev *dev)
955 	ac97_reg_update_bits(dev, AC97_PAGING, 0xf, 0);
957 	val = ac97_reg_cached_read(dev, AC97_ALC650_CLOCK_SOURCE);
960 	ac97_reg_cached_write(dev, AC97_ALC650_CLOCK_SOURCE, val);
962 	ac97_reg_cached_write(dev, AC97_ALC650_MULTI_CHAN_CTRL, 0x8000);
963 	ac97_reg_cached_write(dev, AC97_ALC650_SURR_VOLUME, 0x808);
964 	ac97_reg_cached_write(dev, AC97_ALC650_CEN_LFE_VOLUME, 0x808);
966 	if (dev->codec_id == 0x414c4781)
967 		ac97_reg_update_bits(dev, AC97_ALC650_MISC_CONTROL, 0x800, 0x800);
972 alc850_init(ac97_dev *dev)
976 	ac97_reg_update_bits(dev, AC97_PAGING, 0xf, 0);
978 	ac97_reg_cached_write(dev, AC97_ALC650_MULTI_CHAN_CTRL, 0x8000);
979 	ac97_reg_cached_write(dev, AC97_ALC650_CLOCK_SOURCE, 0x20d2);
980 	ac97_reg_cached_write(dev, AC97_ALC650_GPIO_SETUP, 0x8a90);
981 	ac97_reg_cached_write(dev, AC97_ALC650_SURR_VOLUME, 0x808);
982 	ac97_reg_cached_write(dev, AC97_ALC650_CEN_LFE_VOLUME, 0x808);
987 stac9708_init(ac97_dev *dev)
996 	ac97_reg_cached_write(dev, 0x6C, 0x0000);
998 	ac97_reg_cached_write(dev, 0x74, 0x0000);
1003 stac9721_init(ac97_dev *dev)
1007 	ac97_reg_cached_write(dev, 0x6E, 0x0000);
1009 	ac97_reg_cached_write(dev, 0x70, 0xabba);
1011 	ac97_reg_cached_write(dev, 0x72, 0x0002);
1013 	ac97_reg_cached_write(dev, 0x74, 0x0000);
1015 	ac97_reg_cached_write(dev, 0x76, 0xabba);
1017 	ac97_reg_cached_write(dev, 0x78, 0x0000);
1022 stac9744_init(ac97_dev *dev)
1026 	ac97_reg_cached_write(dev, 0x6E, 0x0000);
1028 	ac97_reg_cached_write(dev, 0x70, 0xabba);
1030 	ac97_reg_cached_write(dev, 0x72, 0x0002);
1032 	ac97_reg_cached_write(dev, 0x74, 0x0000);
1034 	ac97_reg_cached_write(dev, 0x76, 0xabba);
1036 	ac97_reg_cached_write(dev, 0x78, 0x0000);
1041 stac9756_init(ac97_dev *dev)
1045 	ac97_reg_cached_write(dev, 0x6E, 0x1000);
1047 	ac97_reg_cached_write(dev, 0x70, 0xabba);
1049 	ac97_reg_cached_write(dev, 0x72, 0x0002);
1051 	ac97_reg_cached_write(dev, 0x74, 0x0000);
1053 	ac97_reg_cached_write(dev, 0x76, 0xabba);
1055 	ac97_reg_cached_write(dev, 0x78, 0x0000);
1061 stac9758_init(ac97_dev *dev)
1065 	ac97_reg_update_bits(dev, AC97_PAGING, 0xf, 0);
1067 	if (dev->subsystem == 0x107b0601) {
1068 		ac97_reg_cached_write(dev, 0x64, 0xfc70);
1069 		ac97_reg_cached_write(dev, 0x68, 0x2102);
1070 		ac97_reg_cached_write(dev, 0x66, 0x0203);
1071 		ac97_reg_cached_write(dev, 0x72, 0x0041);
1073 		ac97_reg_cached_write(dev, 0x64, 0xd794);
1074 		ac97_reg_cached_write(dev, 0x68, 0x2001);
1075 		ac97_reg_cached_write(dev, 0x66, 0x0201);
1076 		ac97_reg_cached_write(dev, 0x72, 0x0040);
1082 tr28028_init(ac97_dev *dev)
1085 	ac97_reg_cached_write(dev, AC97_POWERDOWN, 0x0300);
1086 	ac97_reg_cached_write(dev, AC97_POWERDOWN, 0x0000);
1087 	ac97_reg_cached_write(dev, AC97_SURR_VOLUME, 0x0000);
1088 	ac97_reg_cached_write(dev, AC97_SPDIF_CONTROL, 0x0000);
1093 wm9701_init(ac97_dev *dev)
1102 	ac97_reg_cached_write(dev, 0x5a, 0x0200);
1107 wm9703_init(ac97_dev *dev)
1111 	ac97_reg_cached_write(dev, 0x72, 0x0808);
1113 	ac97_reg_cached_write(dev, AC97_GENERAL_PURPOSE, 0x8000);
1118 wm9704_init(ac97_dev *dev)
1122 	ac97_reg_cached_write(dev, 0x70, 0x0808);
1124 	ac97_reg_cached_write(dev, 0x72, 0x0808);
1126 	ac97_reg_cached_write(dev, 0x74, 0x0808);
1128 	ac97_reg_cached_write(dev, 0x5a, 0x0200);