Lines Matching refs:bus
11 #include <bus/PCI.h>
75 virtio_pci_find_capability(virtio_pci_sim_info* bus, uint8 cfgType,
79 if (bus->pci->find_pci_capability(bus->device, PCI_cap_id_vendspec, &capabilityOffset) != B_OK)
91 v->reg[i] = bus->pci->read_pci_config(bus->device, capabilityOffset + i * 4, 4);
103 v->reg[i] = bus->pci->read_pci_config(bus->device, capabilityOffset + i * 4, 4);
112 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)data;
114 if (bus->virtio1) {
115 uint8* isrAddr = (uint8*)bus->isrAddr;
118 isr = bus->pci->read_io_8(bus->device,
119 bus->base_addr + VIRTIO_PCI_ISR);
125 gVirtio->config_interrupt_handler(bus->sim);
128 gVirtio->queue_interrupt_handler(bus->sim, INT16_MAX);
137 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)data;
138 gVirtio->config_interrupt_handler(bus->sim);
157 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)data;
158 gVirtio->queue_interrupt_handler(bus->sim, INT16_MAX);
165 virtio_pci_setup_msix_interrupts(virtio_pci_sim_info* bus)
169 if (bus->virtio1) {
170 volatile uint16 *msixVector = (uint16*)(bus->commonCfgAddr
174 bus->pci->write_io_16(bus->device, bus->base_addr
176 if (bus->pci->read_io_16(bus->device, bus->base_addr
182 if (bus->irq_type == VIRTIO_IRQ_MSI_X || bus->irq_type == VIRTIO_IRQ_MSI_X_SHARED)
185 for (uint16 queue = 0; queue < bus->queue_count; queue++) {
186 if (bus->virtio1) {
187 volatile uint16* queueSelect = (uint16*)(bus->commonCfgAddr
190 volatile uint16* msixVector = (uint16*)(bus->commonCfgAddr
194 bus->pci->write_io_16(bus->device, bus->base_addr
196 bus->pci->write_io_16(bus->device, bus->base_addr
199 if (bus->pci->read_io_16(bus->device, bus->base_addr
205 if (bus->irq_type == VIRTIO_IRQ_MSI_X)
217 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
218 bus->sim = sim;
226 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
228 TRACE("read_host_features() %p node %p pci %p device %p\n", bus,
229 bus->node, bus->pci, bus->device);
231 if (bus->virtio1) {
232 volatile uint32 *select = (uint32*)(bus->commonCfgAddr
234 volatile uint32 *feature = (uint32*)(bus->commonCfgAddr
242 *features = bus->pci->read_io_32(bus->device,
243 bus->base_addr + VIRTIO_PCI_HOST_FEATURES);
253 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
254 if (bus->virtio1) {
255 volatile uint32 *select = (uint32*)(bus->commonCfgAddr
257 volatile uint32 *feature = (uint32*)(bus->commonCfgAddr
264 bus->pci->write_io_32(bus->device, bus->base_addr
275 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
276 if (bus->virtio1) {
277 uint8 *addr = (uint8*)(bus->commonCfgAddr
281 return bus->pci->read_io_8(bus->device, bus->base_addr + VIRTIO_PCI_STATUS);
290 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
291 if (bus->virtio1) {
292 uint8 *addr = (uint8*)(bus->commonCfgAddr
301 old = bus->pci->read_io_8(bus->device, bus->base_addr + VIRTIO_PCI_STATUS);
302 bus->pci->write_io_8(bus->device, bus->base_addr + VIRTIO_PCI_STATUS, status | old);
312 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
314 addr_t offset = bus->base_addr + _offset;
315 if (!bus->virtio1)
316 offset += VIRTIO_PCI_CONFIG(bus);
322 if (bus->virtio1) {
325 *buffer = bus->pci->read_io_8(bus->device, offset);
329 if (bus->virtio1) {
332 *(uint16*)buffer = bus->pci->read_io_16(bus->device, offset);
335 if (bus->virtio1) {
338 *(uint32*)buffer = bus->pci->read_io_32(bus->device,
356 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
358 addr_t offset = bus->base_addr + _offset;
359 if (!bus->virtio1)
360 offset += VIRTIO_PCI_CONFIG(bus);
366 if (bus->virtio1) {
369 bus->pci->write_io_8(bus->device, offset, *buffer);
373 if (bus->virtio1) {
376 bus->pci->write_io_16(bus->device, offset, *(const uint16*)buffer);
379 if (bus->virtio1) {
382 bus->pci->write_io_32(bus->device, offset, *(const uint32*)buffer);
397 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
398 if (bus->virtio1) {
399 volatile uint16* queueSelect = (uint16*)(bus->commonCfgAddr
402 volatile uint16* ringSize = (volatile uint16*)(bus->commonCfgAddr
406 bus->pci->write_io_16(bus->device, bus->base_addr + VIRTIO_PCI_QUEUE_SEL,
408 return bus->pci->read_io_16(bus->device, bus->base_addr
419 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
420 if (queue >= bus->queue_count)
423 if (bus->virtio1) {
424 volatile uint16* queueSelect = (uint16*)(bus->commonCfgAddr
428 volatile uint64* queueDesc = (volatile uint64*)(bus->commonCfgAddr
431 volatile uint64* queueAvail = (volatile uint64*)(bus->commonCfgAddr
434 volatile uint64* queueUsed = (volatile uint64*)(bus->commonCfgAddr
437 volatile uint16* queueEnable = (volatile uint16*)(bus->commonCfgAddr
441 volatile uint16* queueNotifyOffset = (volatile uint16*)(bus->commonCfgAddr
443 bus->notifyOffsets[queue] = *queueNotifyOffset * bus->notifyOffsetMultiplier;
445 bus->pci->write_io_16(bus->device, bus->base_addr + VIRTIO_PCI_QUEUE_SEL, queue);
446 bus->pci->write_io_32(bus->device, bus->base_addr + VIRTIO_PCI_QUEUE_PFN,
457 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
458 pci_info *pciInfo = &bus->info;
460 bus->queue_count = queueCount;
463 uint32 msixCount = bus->pci->get_msix_count(bus->device);
468 bus->cookies = new(std::nothrow)
470 if (bus->cookies != NULL
471 && bus->pci->configure_msix(bus->device, vectorCount,
473 && bus->pci->enable_msix(bus->device) == B_OK) {
476 bus->irq = vector;
477 bus->irq_type = VIRTIO_IRQ_MSI_X;
483 if (bus->pci->configure_msix(bus->device, 2, &vector) == B_OK
484 && bus->pci->enable_msix(bus->device) == B_OK) {
486 bus->irq = vector;
487 bus->irq_type = VIRTIO_IRQ_MSI_X_SHARED;
494 if (bus->irq_type == VIRTIO_IRQ_LEGACY) {
495 bus->irq = pciInfo->u.h0.interrupt_line;
496 if (bus->irq == 0xff)
497 bus->irq = 0;
498 TRACE_ALWAYS("using legacy interrupt %" B_PRIu32 "\n", bus->irq);
500 if (bus->irq == 0) {
502 delete bus;
506 if (bus->irq_type != VIRTIO_IRQ_LEGACY) {
507 status_t status = install_io_interrupt_handler(bus->irq,
508 virtio_pci_config_interrupt, bus, 0);
513 int32 irq = bus->irq + 1;
514 if (bus->irq_type == VIRTIO_IRQ_MSI_X) {
516 bus->cookies[queue].sim = bus->sim;
517 bus->cookies[queue].queue = queue;
519 virtio_pci_queue_interrupt, &bus->cookies[queue], 0);
527 virtio_pci_queues_interrupt, bus, 0);
534 virtio_pci_setup_msix_interrupts(bus);
537 status_t status = install_io_interrupt_handler(bus->irq,
538 virtio_pci_interrupt, bus, 0);
554 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
556 if (bus->irq_type != VIRTIO_IRQ_LEGACY) {
557 remove_io_interrupt_handler(bus->irq, virtio_pci_config_interrupt, bus);
558 int32 irq = bus->irq + 1;
559 if (bus->irq_type == VIRTIO_IRQ_MSI_X) {
560 for (int32 queue = 0; queue < bus->queue_count; queue++, irq++)
561 remove_io_interrupt_handler(irq, virtio_pci_queue_interrupt, &bus->cookies[queue]);
562 delete[] bus->cookies;
563 bus->cookies = NULL;
565 remove_io_interrupt_handler(irq, virtio_pci_queues_interrupt, bus);
567 bus->pci->disable_msi(bus->device);
568 bus->pci->unconfigure_msi(bus->device);
570 remove_io_interrupt_handler(bus->irq, virtio_pci_interrupt, bus);
580 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)cookie;
581 if (queue >= bus->queue_count)
583 if (bus->virtio1) {
584 volatile uint16* notifyAddr = (volatile uint16*)(bus->notifyAddr + bus->notifyOffsets[queue]);
587 bus->pci->write_io_16(bus->device, bus->base_addr
602 virtio_pci_sim_info* bus = new(std::nothrow) virtio_pci_sim_info;
603 if (bus == NULL) {
618 bus->node = node;
619 bus->pci = pci;
620 bus->device = device;
621 bus->cookies = NULL;
622 bus->irq_type = VIRTIO_IRQ_LEGACY;
624 pci_info *pciInfo = &bus->info;
627 bus->virtio1 = pciInfo->revision == 1;
629 if (bus->virtio1) {
633 if (virtio_pci_find_capability(bus, VIRTIO_PCI_CAP_COMMON_CFG, &common,
637 if (virtio_pci_find_capability(bus, VIRTIO_PCI_CAP_ISR_CFG, &isr,
641 if (virtio_pci_find_capability(bus, VIRTIO_PCI_CAP_DEVICE_CFG, &deviceCap,
647 if (virtio_pci_find_capability(bus, VIRTIO_PCI_CAP_NOTIFY_CFG, ¬ify,
676 bus->registersArea[i] = map_physical_memory("Virtio PCI memory mapped registers",
682 bus->commonCfgAddr = registers[common.bar] + common.offset;
683 bus->isrAddr = registers[isr.bar] + isr.offset;
684 bus->notifyAddr = registers[notify.cap.bar] + notify.cap.offset;
685 bus->notifyOffsetMultiplier = notify.notify_off_multiplier;
687 bus->base_addr = registers[deviceCap.bar] + deviceCap.offset;
689 // enable bus master and memory
695 volatile uint16 *queueCount = (uint16*)(bus->commonCfgAddr
697 bus->notifyOffsets = new addr_t[*queueCount];
701 bus->base_addr = pciInfo->u.h0.base_registers[0];
703 // enable bus master and io
711 set_status(bus, VIRTIO_CONFIG_STATUS_RESET);
712 set_status(bus, VIRTIO_CONFIG_STATUS_ACK);
714 TRACE("init_bus() %p node %p pci %p device %p\n", bus, node,
715 bus->pci, bus->device);
717 *bus_cookie = bus;
725 virtio_pci_sim_info* bus = (virtio_pci_sim_info*)bus_cookie;
726 if (bus->irq_type != VIRTIO_IRQ_LEGACY) {
727 int32 irq = bus->irq + 1;
728 if (bus->irq_type == VIRTIO_IRQ_MSI_X) {
729 for (int32 queue = 0; queue < bus->queue_count; queue++, irq++)
730 remove_io_interrupt_handler(irq, virtio_pci_queue_interrupt, &bus->cookies[queue]);
731 delete[] bus->cookies;
733 remove_io_interrupt_handler(irq, virtio_pci_queues_interrupt, bus);
735 remove_io_interrupt_handler(bus->irq, virtio_pci_config_interrupt,
736 bus);
738 bus->pci->disable_msi(bus->device);
739 bus->pci->unconfigure_msi(bus->device);
741 remove_io_interrupt_handler(bus->irq, virtio_pci_interrupt, bus);
743 if (bus->virtio1) {
745 if (bus->registersArea[i] >= 0)
746 delete_area(bus->registersArea[i]);
750 delete[] bus->notifyOffsets;
753 delete bus;
790 // properties of this controller for virtio bus manager
837 const char* bus;
841 if (gDeviceManager->get_attr_string(parent, B_DEVICE_BUS, &bus, false) != B_OK
849 if (strcmp(bus, "pci") != 0)