i2c/pch/pch_i2c.cpp

14 #include <bus/PCI.h>
26 enable_device(pch_i2c_sim_info* bus, bool enable)
30 		write32(bus->registers + PCH_IC_ENABLE, status);
31 		if ((read32(bus->registers + PCH_IC_ENABLE_STATUS) & 1) == status)
41 pch_i2c_interrupt_handler(pch_i2c_sim_info* bus)
46 	uint32 enable = read32(bus->registers + PCH_IC_ENABLE);
50 	uint32 status = read32(bus->registers + PCH_IC_INTR_STAT);
52 		write32(bus->registers + PCH_IC_CLR_RX_UNDER, 0);
54 		write32(bus->registers + PCH_IC_CLR_RX_OVER, 0);
56 		write32(bus->registers + PCH_IC_CLR_TX_OVER, 0);
58 		write32(bus->registers + PCH_IC_CLR_RD_REQ, 0);
60 		write32(bus->registers + PCH_IC_CLR_TX_ABRT, 0);
62 		write32(bus->registers + PCH_IC_CLR_RX_DONE, 0);
64 		write32(bus->registers + PCH_IC_CLR_ACTIVITY, 0);
66 		write32(bus->registers + PCH_IC_CLR_STOP_DET, 0);
68 		write32(bus->registers + PCH_IC_CLR_START_DET, 0);
70 		write32(bus->registers + PCH_IC_CLR_GEN_CALL, 0);
79 		ConditionVariable::NotifyAll(&bus->readwait, B_OK);
81 		ConditionVariable::NotifyAll(&bus->writewait, B_OK);
83 		bus->busy = 0;
84 		ConditionVariable::NotifyAll(&bus->busy, B_OK);
98 	pch_i2c_sim_info* bus = (pch_i2c_sim_info*)cookie;
99 	bus->sim = sim;
109 	pch_i2c_sim_info* bus = (pch_i2c_sim_info*)cookie;
111 	if (atomic_test_and_set(&bus->busy, 1, 0) != 0)
118 		status = read32(bus->registers + PCH_IC_STATUS);
125 		bus->busy = 0;
131 	enable_device(bus, false);
132 	write32(bus->registers + PCH_IC_CON,
133 		read32(bus->registers + PCH_IC_CON) & ~PCH_IC_CON_10BIT_ADDR_MASTER);
134 	write32(bus->registers + PCH_IC_TAR, slaveAddress);
136 	write32(bus->registers + PCH_IC_INTR_MASK, 0);
137 	read32(bus->registers + PCH_IC_CLR_INTR);
139 	enable_device(bus, true);
141 	read32(bus->registers + PCH_IC_CLR_INTR);
142 	write32(bus->registers + PCH_IC_INTR_MASK, PCH_IC_INTR_STAT_TX_EMPTY);
149 		uint16 txLimit = bus->tx_fifo_depth
150 			- read32(bus->registers + PCH_IC_TXFLR);
154 			bus->busy = 0;
163 			write32(bus->registers + PCH_IC_DATA_CMD, cmd);
169 	uint16 txLimit = bus->tx_fifo_depth
170 		- read32(bus->registers + PCH_IC_TXFLR);
185 		write32(bus->registers + PCH_IC_DATA_CMD, cmd);
194 			write32(bus->registers + PCH_IC_INTR_MASK,
199 			condition.Publish(&bus->readwait, "pch_i2c");
201 			status_t status = variableEntry.Wait(&bus->readwait,
206 			uint32 rxBytes = read32(bus->registers + PCH_IC_RXFLR);
210 				bus->busy = 0;
214 				uint32 read = read32(bus->registers + PCH_IC_DATA_CMD);
226 			txLimit = bus->tx_fifo_depth
227 				- read32(bus->registers + PCH_IC_TXFLR);
234 		while (bus->busy == 1) {
235 			write32(bus->registers + PCH_IC_INTR_MASK,
240 			condition.Publish(&bus->busy, "pch_i2c");
242 			err = variableEntry.Wait(&bus->busy, B_RELATIVE_TIMEOUT,
251 	bus->busy = 0;
309 	pch_i2c_sim_info* bus = (pch_i2c_sim_info*)context;
347 	status = gI2c->register_device(bus->sim, crs.i2c_addr, hid, cidList,
364 	pch_i2c_sim_info* bus = (pch_i2c_sim_info*)cookie;
365 	if (bus->scan_bus != NULL)
366 		return bus->scan_bus(bus);
375 	pch_i2c_sim_info* bus = (pch_i2c_sim_info*)cookie;
376 	return mutex_lock(&bus->lock);
384 	pch_i2c_sim_info* bus = (pch_i2c_sim_info*)cookie;
385 	mutex_unlock(&bus->lock);
399 	pch_i2c_sim_info* bus;
401 	gDeviceManager->get_driver(parent, &driver, (void**)&bus);
405 		" irq 0x%" B_PRIx32 "\n", bus->base_addr, bus->map_size, bus->irq);
407 	bus->registersArea = map_physical_memory("PCHI2C memory mapped registers",
408 		bus->base_addr, bus->map_size, B_ANY_KERNEL_ADDRESS,
410 		(void **)&bus->registers);
411 	// init bus
412 	bus->capabilities = read32(bus->registers + PCH_SUP_CAPABLITIES);
414 		(bus->capabilities >> PCH_SUP_CAPABLITIES_TYPE_SHIFT)
416 		bus->capabilities);
417 	if (((bus->capabilities >> PCH_SUP_CAPABLITIES_TYPE_SHIFT)
424 	write32(bus->registers + PCH_SUP_RESETS, 0);
425 	write32(bus->registers + PCH_SUP_RESETS,
428 	if (bus->ss_hcnt == 0)
429 		bus->ss_hcnt = read32(bus->registers + PCH_IC_SS_SCL_HCNT);
430 	if (bus->ss_lcnt == 0)
431 		bus->ss_lcnt = read32(bus->registers + PCH_IC_SS_SCL_LCNT);
432 	if (bus->fs_hcnt == 0)
433 		bus->fs_hcnt = read32(bus->registers + PCH_IC_FS_SCL_HCNT);
434 	if (bus->fs_lcnt == 0)
435 		bus->fs_lcnt = read32(bus->registers + PCH_IC_FS_SCL_LCNT);
436 	if (bus->sda_hold_time == 0)
437 		bus->sda_hold_time = read32(bus->registers + PCH_IC_SDA_HOLD);
439 		" 0x%04" B_PRIx16 " 0x%08" B_PRIx32 "\n", bus->ss_hcnt, bus->ss_lcnt,
440 		bus->fs_hcnt, bus->fs_lcnt, bus->sda_hold_time);
442 	enable_device(bus, false);
444 	write32(bus->registers + PCH_IC_SS_SCL_HCNT, bus->ss_hcnt);
445 	write32(bus->registers + PCH_IC_SS_SCL_LCNT, bus->ss_lcnt);
446 	write32(bus->registers + PCH_IC_FS_SCL_HCNT, bus->fs_hcnt);
447 	write32(bus->registers + PCH_IC_FS_SCL_LCNT, bus->fs_lcnt);
448 	if (bus->hs_hcnt > 0)
449 		write32(bus->registers + PCH_IC_HS_SCL_HCNT, bus->hs_hcnt);
450 	if (bus->hs_lcnt > 0)
451 		write32(bus->registers + PCH_IC_HS_SCL_LCNT, bus->hs_lcnt);
453 		uint32 reg = read32(bus->registers + PCH_IC_COMP_VERSION);
455 			write32(bus->registers + PCH_IC_SDA_HOLD, bus->sda_hold_time);
459 		bus->tx_fifo_depth = 32;
460 		bus->rx_fifo_depth = 32;
461 		uint32 reg = read32(bus->registers + PCH_IC_COMP_PARAM1);
464 		if (rx_fifo_depth > 1 && rx_fifo_depth < bus->rx_fifo_depth)
465 			bus->rx_fifo_depth = rx_fifo_depth;
466 		if (tx_fifo_depth > 1 && tx_fifo_depth < bus->tx_fifo_depth)
467 			bus->tx_fifo_depth = tx_fifo_depth;
468 		write32(bus->registers + PCH_IC_RX_TL, 0);
469 		write32(bus->registers + PCH_IC_TX_TL, bus->tx_fifo_depth / 2);
472 	bus->masterConfig = PCH_IC_CON_MASTER | PCH_IC_CON_SLAVE_DISABLE |
474 	write32(bus->registers + PCH_IC_CON, bus->masterConfig);
476 	write32(bus->registers + PCH_IC_INTR_MASK, 0);
477 	read32(bus->registers + PCH_IC_CLR_INTR);
479 	status = install_io_interrupt_handler(bus->irq,
480 		(interrupt_handler)pch_i2c_interrupt_handler, bus, 0);
486 	mutex_init(&bus->lock, "pch_i2c");
487 	*bus_cookie = bus;
491 	if (bus->registersArea >= 0)
492 		delete_area(bus->registersArea);
500 	pch_i2c_sim_info* bus = (pch_i2c_sim_info*)bus_cookie;
502 	mutex_destroy(&bus->lock);
503 	remove_io_interrupt_handler(bus->irq,
504 		(interrupt_handler)pch_i2c_interrupt_handler, bus);
505 	if (bus->registersArea >= 0)
506 		delete_area(bus->registersArea);