Lines Matching refs:dev
777 PCIDev *dev = bus->child;
778 while (dev) {
780 *outInfo = dev->info;
784 if (dev->child && B_OK == _GetNthInfo(dev->child, currentIndex,
787 dev = dev->next;
802 for (int dev = 0; dev < maxBusDevices; dev++) {
803 uint16 vendor_id = ReadConfig(domain, bus, dev, 0, PCI_vendor_id, 2);
807 int numFunctions = _NumFunctions(domain, bus, dev);
809 uint16 device_id = ReadConfig(domain, bus, dev, function,
814 uint8 baseClass = ReadConfig(domain, bus, dev, function,
816 uint8 subClass = ReadConfig(domain, bus, dev, function,
822 uint8 headerType = ReadConfig(domain, bus, dev, function,
827 TRACE(("PCI: found PCI-PCI bridge: domain %u, bus %u, dev %u, func %u\n",
828 domain, bus, dev, function));
832 ReadConfig(domain, bus, dev, function, PCI_command, 2),
833 ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
834 ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
835 ReadConfig(domain, bus, dev, function, PCI_subordinate_bus, 1)));
839 pcicmd = ReadConfig(domain, bus, dev, function, PCI_command, 2);
842 WriteConfig(domain, bus, dev, function, PCI_command, 2, pcicmd);
845 WriteConfig(domain, bus, dev, function, PCI_primary_bus, 1, 0);
846 WriteConfig(domain, bus, dev, function, PCI_secondary_bus, 1, 0);
847 WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, 0);
852 ReadConfig(domain, bus, dev, function, PCI_command, 2),
853 ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
854 ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
855 ReadConfig(domain, bus, dev, function, PCI_subordinate_bus, 1)));
862 for (int dev = 0; dev < maxBusDevices; dev++) {
863 uint16 vendor_id = ReadConfig(domain, bus, dev, 0, PCI_vendor_id, 2);
867 int numFunctions = _NumFunctions(domain, bus, dev);
869 uint16 deviceID = ReadConfig(domain, bus, dev, function,
874 uint8 baseClass = ReadConfig(domain, bus, dev, function,
876 uint8 subClass = ReadConfig(domain, bus, dev, function,
882 uint8 headerType = ReadConfig(domain, bus, dev, function,
887 TRACE(("PCI: configuring PCI-PCI bridge: domain %u, bus %u, dev %u, func %u\n",
888 domain, bus, dev, function));
891 WriteConfig(domain, bus, dev, function, PCI_primary_bus, 1, bus);
892 WriteConfig(domain, bus, dev, function, PCI_secondary_bus, 1,
894 WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, 255);
898 pcicmd = ReadConfig(domain, bus, dev, function, PCI_command, 2);
900 WriteConfig(domain, bus, dev, function, PCI_command, 2, pcicmd);
905 ReadConfig(domain, bus, dev, function, PCI_command, 2),
906 ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
907 ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
908 ReadConfig(domain, bus, dev, function, PCI_subordinate_bus, 1)));
914 WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, lastUsedBusNumber);
919 ReadConfig(domain, bus, dev, function, PCI_command, 2),
920 ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
921 ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
922 ReadConfig(domain, bus, dev, function, PCI_subordinate_bus, 1)));
948 for (int dev = 0; dev < maxBusDevices; dev++) {
949 uint16 vendorId = ReadConfig(domain, bus, dev, 0, PCI_vendor_id, 2);
953 int numFunctions = _NumFunctions(domain, bus, dev);
955 uint16 deviceId = ReadConfig(domain, bus, dev, function,
960 pci_fixup_device(this, domain, bus, dev, function);
962 uint8 baseClass = ReadConfig(domain, bus, dev, function,
966 uint8 subClass = ReadConfig(domain, bus, dev, function,
973 uint8 headerType = ReadConfig(domain, bus, dev, function,
976 dprintf("PCI: dom %u, bus %u, dev %2u, func %u, PCI bridge"
978 domain, bus, dev, function, headerType);
983 int busBehindBridge = ReadConfig(domain, bus, dev, function,
998 for (PCIDev *dev = bus->child; dev; dev = dev->next) {
999 if (dev->info.class_base == PCI_bridge
1000 && dev->info.class_sub == PCI_pci
1001 && (dev->info.header_type & PCI_header_type_mask)
1003 uint16 bridgeControlOld = ReadConfig(dev->domain, dev->bus,
1004 dev->device, dev->function, PCI_bridge_control, 2);
1016 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1018 bridgeControlNew = ReadConfig(dev->domain, dev->bus, dev->device,
1019 dev->function, PCI_bridge_control, 2);
1020 dprintf("PCI: dom %u, bus %u, dev %2u, func %u, changed PCI bridge"
1021 " control from 0x%04x to 0x%04x\n", dev->domain, dev->bus,
1022 dev->device, dev->function, bridgeControlOld,
1026 if (dev->child)
1027 _ConfigureBridges(dev->child);
1035 for (PCIDev *dev = bus->child; dev; dev = dev->next) {
1037 uint16 status = ReadConfig(dev->domain, dev->bus, dev->device,
1038 dev->function, PCI_status, 2);
1039 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1042 kprintf("domain %u, bus %u, dev %2u, func %u, PCI device status "
1043 "0x%04x\n", dev->domain, dev->bus, dev->device, dev->function,
1059 if (dev->info.class_base == PCI_bridge
1060 && dev->info.class_sub == PCI_pci) {
1062 uint16 secondaryStatus = ReadConfig(dev->domain, dev->bus,
1063 dev->device, dev->function, PCI_secondary_status, 2);
1064 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1067 kprintf("domain %u, bus %u, dev %2u, func %u, PCI bridge "
1068 "secondary status 0x%04x\n", dev->domain, dev->bus,
1069 dev->device, dev->function, secondaryStatus);
1085 uint16 bridgeControl = ReadConfig(dev->domain, dev->bus,
1086 dev->device, dev->function, PCI_bridge_control, 2);
1087 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1090 kprintf("domain %u, bus %u, dev %2u, func %u, PCI bridge "
1091 "control 0x%04x\n", dev->domain, dev->bus, dev->device,
1092 dev->function, bridgeControl);
1099 if (dev->child)
1100 ClearDeviceStatus(dev->child, dumpStatus);
1121 for (int dev = 0; dev < maxBusDevices; dev++) {
1122 uint16 vendorID = ReadConfig(bus->domain, bus->bus, dev, 0,
1127 int numFunctions = _NumFunctions(bus->domain, bus->bus, dev);
1129 _DiscoverDevice(bus, dev, function);
1137 PCI::_DiscoverDevice(PCIBus *bus, uint8 dev, uint8 function)
1139 FLOW("PCI: DiscoverDevice, domain %u, bus %u, dev %u, func %u\n", bus->domain, bus->bus, dev, function);
1141 uint16 deviceID = ReadConfig(bus->domain, bus->bus, dev, function,
1146 PCIDev *newDev = _CreateDevice(bus, dev, function);
1148 uint8 baseClass = ReadConfig(bus->domain, bus->bus, dev, function,
1150 uint8 subClass = ReadConfig(bus->domain, bus->bus, dev, function,
1152 uint8 headerType = ReadConfig(bus->domain, bus->bus, dev, function,
1156 uint8 secondaryBus = ReadConfig(bus->domain, bus->bus, dev, function,
1186 FLOW("PCI: CreateDevice, domain %u, bus %u, dev %u, func %u:\n", parent->domain,
1237 PCI::_GetBarInfo(PCIDev *dev, uint8 offset, uint32 &_ramAddress,
1241 uint64 pciAddress = ReadConfig(dev->domain, dev->bus, dev->device,
1242 dev->function, offset, 4);
1243 WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1245 uint64 size = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1247 WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1258 uint64 highPCIAddress = ReadConfig(dev->domain, dev->bus,
1259 dev->device, dev->function, offset + 4, 4);
1260 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1262 uint64 highSize = ReadConfig(dev->domain, dev->bus, dev->device,
1263 dev->function, offset + 4, 4);
1264 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1298 PCI::_GetRomBarInfo(PCIDev *dev, uint8 offset, uint32 &_address, uint32 *_size,
1301 uint32 oldValue = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1303 WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1305 uint32 newValue = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1307 WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1319 PCI::_ReadBasicInfo(PCIDev *dev)
1323 if (_CreateVirtualBus(dev->domain, dev->bus, &virtualBus) != B_OK) {
1324 dprintf("PCI: CreateVirtualBus failed, domain %u, bus %u\n", dev->domain, dev->bus);
1328 dev->info.vendor_id = ReadConfig(dev->domain, dev->bus, dev->device,
1329 dev->function, PCI_vendor_id, 2);
1330 dev->info.device_id = ReadConfig(dev->domain, dev->bus, dev->device,
1331 dev->function, PCI_device_id, 2);
1332 dev->info.bus = virtualBus;
1333 dev->info.device = dev->device;
1334 dev->info.function = dev->function;
1335 dev->info.revision = ReadConfig(dev->domain, dev->bus, dev->device,
1336 dev->function, PCI_revision, 1);
1337 dev->info.class_api = ReadConfig(dev->domain, dev->bus, dev->device,
1338 dev->function, PCI_class_api, 1);
1339 dev->info.class_sub = ReadConfig(dev->domain, dev->bus, dev->device,
1340 dev->function, PCI_class_sub, 1);
1341 dev->info.class_base = ReadConfig(dev->domain, dev->bus, dev->device,
1342 dev->function, PCI_class_base, 1);
1343 dev->info.line_size = ReadConfig(dev->domain, dev->bus, dev->device,
1344 dev->function, PCI_line_size, 1);
1345 dev->info.latency = ReadConfig(dev->domain, dev->bus, dev->device,
1346 dev->function, PCI_latency, 1);
1349 dev->info.header_type = ReadConfig(dev->domain, dev->bus, dev->device,
1350 dev->function, PCI_header_type, 1);
1351 dev->info.bist = ReadConfig(dev->domain, dev->bus, dev->device,
1352 dev->function, PCI_bist, 1);
1353 dev->info.reserved = 0;
1358 PCI::_ReadHeaderInfo(PCIDev *dev)
1360 switch (dev->info.header_type & PCI_header_type_mask) {
1365 uint16 pcicmd = ReadConfig(dev->domain, dev->bus, dev->device,
1366 dev->function, PCI_command, 2);
1367 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1372 _GetRomBarInfo(dev, PCI_rom_base, dev->info.u.h0.rom_base_pci,
1373 &dev->info.u.h0.rom_size);
1375 i += _GetBarInfo(dev, PCI_base_registers + 4 * i,
1376 dev->info.u.h0.base_registers[i],
1377 dev->info.u.h0.base_registers_pci[i],
1378 dev->info.u.h0.base_register_sizes[i],
1379 dev->info.u.h0.base_register_flags[i],
1380 i < 5 ? &dev->info.u.h0.base_registers[i + 1] : NULL,
1381 i < 5 ? &dev->info.u.h0.base_registers_pci[i + 1] : NULL,
1382 i < 5 ? &dev->info.u.h0.base_register_sizes[i + 1] : NULL);
1386 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1389 dev->info.u.h0.rom_base = (uint32)pci_ram_address(
1390 dev->info.u.h0.rom_base_pci);
1392 dev->info.u.h0.cardbus_cis = ReadConfig(dev->domain, dev->bus,
1393 dev->device, dev->function, PCI_cardbus_cis, 4);
1394 dev->info.u.h0.subsystem_id = ReadConfig(dev->domain, dev->bus,
1395 dev->device, dev->function, PCI_subsystem_id, 2);
1396 dev->info.u.h0.subsystem_vendor_id = ReadConfig(dev->domain,
1397 dev->bus, dev->device, dev->function, PCI_subsystem_vendor_id,
1399 dev->info.u.h0.interrupt_line = ReadConfig(dev->domain, dev->bus,
1400 dev->device, dev->function, PCI_interrupt_line, 1);
1401 dev->info.u.h0.interrupt_pin = ReadConfig(dev->domain, dev->bus,
1402 dev->device, dev->function, PCI_interrupt_pin, 1);
1403 dev->info.u.h0.min_grant = ReadConfig(dev->domain, dev->bus,
1404 dev->device, dev->function, PCI_min_grant, 1);
1405 dev->info.u.h0.max_latency = ReadConfig(dev->domain, dev->bus,
1406 dev->device, dev->function, PCI_max_latency, 1);
1414 uint16 pcicmd = ReadConfig(dev->domain, dev->bus, dev->device,
1415 dev->function, PCI_command, 2);
1416 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1420 _GetRomBarInfo(dev, PCI_bridge_rom_base,
1421 dev->info.u.h1.rom_base_pci);
1423 i += _GetBarInfo(dev, PCI_base_registers + 4 * i,
1424 dev->info.u.h1.base_registers[i],
1425 dev->info.u.h1.base_registers_pci[i],
1426 dev->info.u.h1.base_register_sizes[i],
1427 dev->info.u.h1.base_register_flags[i],
1428 i < 1 ? &dev->info.u.h1.base_registers[i + 1] : NULL,
1429 i < 1 ? &dev->info.u.h1.base_registers_pci[i + 1] : NULL,
1430 i < 1 ? &dev->info.u.h1.base_register_sizes[i + 1] : NULL);
1434 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1437 dev->info.u.h1.rom_base = (uint32)pci_ram_address(
1438 dev->info.u.h1.rom_base_pci);
1440 dev->info.u.h1.primary_bus = ReadConfig(dev->domain, dev->bus,
1441 dev->device, dev->function, PCI_primary_bus, 1);
1442 dev->info.u.h1.secondary_bus = ReadConfig(dev->domain, dev->bus,
1443 dev->device, dev->function, PCI_secondary_bus, 1);
1444 dev->info.u.h1.subordinate_bus = ReadConfig(dev->domain,
1445 dev->bus, dev->device, dev->function, PCI_subordinate_bus, 1);
1446 dev->info.u.h1.secondary_latency = ReadConfig(dev->domain,
1447 dev->bus, dev->device, dev->function, PCI_secondary_latency, 1);
1448 dev->info.u.h1.io_base = ReadConfig(dev->domain, dev->bus,
1449 dev->device, dev->function, PCI_io_base, 1);
1450 dev->info.u.h1.io_limit = ReadConfig(dev->domain, dev->bus,
1451 dev->device, dev->function, PCI_io_limit, 1);
1452 dev->info.u.h1.secondary_status = ReadConfig(dev->domain,
1453 dev->bus, dev->device, dev->function, PCI_secondary_status, 2);
1454 dev->info.u.h1.memory_base = ReadConfig(dev->domain, dev->bus,
1455 dev->device, dev->function, PCI_memory_base, 2);
1456 dev->info.u.h1.memory_limit = ReadConfig(dev->domain, dev->bus,
1457 dev->device, dev->function, PCI_memory_limit, 2);
1458 dev->info.u.h1.prefetchable_memory_base = ReadConfig(dev->domain,
1459 dev->bus, dev->device, dev->function,
1461 dev->info.u.h1.prefetchable_memory_limit = ReadConfig(
1462 dev->domain, dev->bus, dev->device, dev->function,
1464 dev->info.u.h1.prefetchable_memory_base_upper32 = ReadConfig(
1465 dev->domain, dev->bus, dev->device, dev->function,
1467 dev->info.u.h1.prefetchable_memory_limit_upper32 = ReadConfig(
1468 dev->domain, dev->bus, dev->device, dev->function,
1470 dev->info.u.h1.io_base_upper16 = ReadConfig(dev->domain,
1471 dev->bus, dev->device, dev->function, PCI_io_base_upper16, 2);
1472 dev->info.u.h1.io_limit_upper16 = ReadConfig(dev->domain,
1473 dev->bus, dev->device, dev->function, PCI_io_limit_upper16, 2);
1474 dev->info.u.h1.interrupt_line = ReadConfig(dev->domain, dev->bus,
1475 dev->device, dev->function, PCI_interrupt_line, 1);
1476 dev->info.u.h1.interrupt_pin = ReadConfig(dev->domain, dev->bus,
1477 dev->device, dev->function, PCI_interrupt_pin, 1);
1478 dev->info.u.h1.bridge_control = ReadConfig(dev->domain, dev->bus,
1479 dev->device, dev->function, PCI_bridge_control, 2);
1480 dev->info.u.h1.subsystem_id = ReadConfig(dev->domain, dev->bus,
1481 dev->device, dev->function, PCI_sub_device_id_1, 2);
1482 dev->info.u.h1.subsystem_vendor_id = ReadConfig(dev->domain,
1483 dev->bus, dev->device, dev->function, PCI_sub_vendor_id_1, 2);
1490 dev->info.u.h2.subsystem_id = ReadConfig(dev->domain, dev->bus,
1491 dev->device, dev->function, PCI_sub_device_id_2, 2);
1492 dev->info.u.h2.subsystem_vendor_id = ReadConfig(dev->domain,
1493 dev->bus, dev->device, dev->function, PCI_sub_vendor_id_2, 2);
1494 dev->info.u.h2.primary_bus = ReadConfig(dev->domain, dev->bus,
1495 dev->device, dev->function, PCI_primary_bus_2, 1);
1496 dev->info.u.h2.secondary_bus = ReadConfig(dev->domain, dev->bus,
1497 dev->device, dev->function, PCI_secondary_bus_2, 1);
1498 dev->info.u.h2.subordinate_bus = ReadConfig(dev->domain,
1499 dev->bus, dev->device, dev->function, PCI_subordinate_bus_2, 1);
1500 dev->info.u.h2.secondary_latency = ReadConfig(dev->domain,
1501 dev->bus, dev->device, dev->function, PCI_secondary_latency_2, 1);
1502 dev->info.u.h2.reserved = 0;
1503 dev->info.u.h2.memory_base = ReadConfig(dev->domain, dev->bus,
1504 dev->device, dev->function, PCI_memory_base0_2, 4);
1505 dev->info.u.h2.memory_limit = ReadConfig(dev->domain, dev->bus,
1506 dev->device, dev->function, PCI_memory_limit0_2, 4);
1507 dev->info.u.h2.memory_base_upper32 = ReadConfig(dev->domain,
1508 dev->bus, dev->device, dev->function, PCI_memory_base1_2, 4);
1509 dev->info.u.h2.memory_limit_upper32 = ReadConfig(dev->domain,
1510 dev->bus, dev->device, dev->function, PCI_memory_limit1_2, 4);
1511 dev->info.u.h2.io_base = ReadConfig(dev->domain, dev->bus,
1512 dev->device, dev->function, PCI_io_base0_2, 4);
1513 dev->info.u.h2.io_limit = ReadConfig(dev->domain, dev->bus,
1514 dev->device, dev->function, PCI_io_limit0_2, 4);
1515 dev->info.u.h2.io_base_upper32 = ReadConfig(dev->domain,
1516 dev->bus, dev->device, dev->function, PCI_io_base1_2, 4);
1517 dev->info.u.h2.io_limit_upper32 = ReadConfig(dev->domain,
1518 dev->bus, dev->device, dev->function, PCI_io_limit1_2, 4);
1519 dev->info.u.h2.secondary_status = ReadConfig(dev->domain,
1520 dev->bus, dev->device, dev->function, PCI_secondary_status_2, 2);
1521 dev->info.u.h2.bridge_control = ReadConfig(dev->domain,
1522 dev->bus, dev->device, dev->function, PCI_bridge_control_2, 2);
1527 TRACE(("PCI: Header type unknown (0x%02x)\n", dev->info.header_type));
1544 for (PCIDev *dev = bus->child; dev; dev = dev->next) {
1545 _ReadBasicInfo(dev);
1546 _ReadHeaderInfo(dev);
1547 _ReadMSIInfo(dev);
1548 _ReadMSIXInfo(dev);
1549 _ReadHtMappingInfo(dev);
1550 if (dev->child)
1551 _RefreshDeviceInfo(dev->child);