Lines Matching defs:stat
79 "No stat","Undef","long","miss Ack err",
295 uint32_t fun, stat;
319 stat = OREAD(sc, FWOHCI_INTSTAT);
320 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
1086 u_int stat, status;
1127 stat = status & FWOHCIEV_MASK;
1128 switch(stat){
1136 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1141 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1156 stat, fwohcicode[stat]);
1178 } else if (stat != FWOHCIEV_ACKPEND) {
1179 if (stat != FWOHCIEV_ACKCOMPL)
1587 uint32_t stat;
1641 stat = OREAD(sc, OHCI_ITCTL(dmach));
1642 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1643 printf("stat 0x%x\n", stat);
1645 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1660 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1665 if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1691 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1693 "IT DMA underrun (0x%08x)\n", stat);
1706 uint32_t stat;
1773 stat = OREAD(sc, OHCI_IRCTL(dmach));
1774 if (stat & OHCI_CNTL_DMA_ACTIVE)
1776 if (stat & OHCI_CNTL_DMA_RUN) {
1778 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1782 printf("start IR DMA 0x%x\n", stat);
1837 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat)
1839 if(stat & OREAD(sc, FWOHCI_INTMASK))
1841 stat & OHCI_INT_EN ? "DMA_EN ":"",
1842 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1843 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1844 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1845 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1846 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1847 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1848 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1849 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1850 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1851 stat & OHCI_INT_PHY_SID ? "SID ":"",
1852 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1853 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1854 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1855 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1856 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1857 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1858 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1859 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1860 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1861 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1862 stat, OREAD(sc, FWOHCI_INTMASK)
1867 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count)
1873 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1891 if (stat & OHCI_INT_PHY_SID) {
1944 // if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active))
1946 if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)))
1951 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count)
1957 if (stat & OHCI_INT_DMA_IR) {
1973 if (stat & OHCI_INT_DMA_IT) {
1981 if (stat & OHCI_INT_DMA_PRRS) {
1988 if (stat & OHCI_INT_DMA_PRRQ) {
1995 if (stat & OHCI_INT_CYC_LOST) {
2008 if (stat & OHCI_INT_DMA_ATRQ) {
2011 if (stat & OHCI_INT_DMA_ATRS) {
2014 if (stat & OHCI_INT_PW_ERR) {
2017 if (stat & OHCI_INT_ERR) {
2020 if (stat & OHCI_INT_PHY_INT) {
2085 uint32_t stat;
2088 stat = atomic_readandclear_int(&sc->intstat);
2089 if (stat)
2090 fwohci_intr_dma(sc, stat, -1);
2099 uint32_t stat, irstat, itstat;
2102 stat = OREAD(sc, FWOHCI_INTSTAT);
2103 if (stat == 0xffffffff) {
2108 if (stat)
2109 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);
2111 stat &= sc->intmask;
2112 if (stat == 0)
2115 atomic_set_int(&sc->intstat, stat);
2116 if (stat & OHCI_INT_DMA_IR) {
2121 if (stat & OHCI_INT_DMA_IT) {
2127 fwohci_intr_core(sc, stat, -1);
2177 uint32_t stat, count;
2189 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2195 if (stat == 0)
2198 switch (stat & FWOHCIEV_MASK){
2206 stat, fwohcicode[stat & 0x1f]);
2224 uint32_t stat;
2239 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2241 if (stat == 0)
2258 switch (stat & FWOHCIEV_MASK) {
2266 stat, fwohcicode[stat & 0x1f]);
2285 uint32_t off, cntl, stat, cmd, match;
2300 cntl = stat = OREAD(sc, off);
2309 stat &= 0xffff ;
2310 if (stat) {
2313 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2314 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2315 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2316 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2317 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2318 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2319 fwohcicode[stat & 0x1f],
2320 stat & 0x1f
2409 fwohcireg_t stat;
2434 stat = res >> OHCI_STATUS_SHIFT;
2444 stat,
2446 if(stat & 0xff00){
2448 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2449 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2450 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2451 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2452 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2453 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2454 fwohcicode[stat & 0x1f],
2455 stat & 0x1f
2745 uint32_t stat, off, status, event;
2882 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
2884 printf("plen: %d, stat %x\n",
2885 plen ,stat);
2887 spd = (stat >> 21) & 0x3;
2888 event = (stat >> 16) & 0x1f;
2918 " tcode=0x%x, stat=0x%08x\n",
2922 fp->mode.common.tcode, stat);