accelerants/radeon_hd/gpu.cpp

100 	if ((Read32(OUT, GRBM_STATUS) & GUI_ACTIVE) == 0)
113 		Write32(OUT, CP_ME_CNTL, CP_ME_HALT);
160 		if ((Read32(OUT, GRBM_STATUS) & grbmBusyMask) != 0
161 			|| (Read32(OUT, GRBM_STATUS2) & grbm2BusyMask) != 0) {
175 			Write32(OUT, GRBM_SOFT_RESET, tmp);
176 			Read32(OUT, GRBM_SOFT_RESET);
178 			Write32(OUT, GRBM_SOFT_RESET, 0);
183 		Write32(OUT, GRBM_SOFT_RESET, tmp);
184 		Read32(OUT, GRBM_SOFT_RESET);
186 		Write32(OUT, GRBM_SOFT_RESET, 0);
193 		Write32(OUT, CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
211 		Write32(OUT, GRBM_SOFT_RESET, grbmReset);
212 		Read32(OUT, GRBM_SOFT_RESET);
215 		Write32(OUT, GRBM_SOFT_RESET, 0);
216 		Read32(OUT, GRBM_SOFT_RESET);
273 	gpuState->d1vgaControl = Read32(OUT, AVIVO_D1VGA_CONTROL);
274 	gpuState->d2vgaControl = Read32(OUT, AVIVO_D2VGA_CONTROL);
275 	gpuState->vgaRenderControl = Read32(OUT, AVIVO_VGA_RENDER_CONTROL);
276 	gpuState->vgaHdpControl = Read32(OUT, AVIVO_VGA_HDP_CONTROL);
277 	gpuState->d1crtcControl = Read32(OUT, AVIVO_D1CRTC_CONTROL);
278 	gpuState->d2crtcControl = Read32(OUT, AVIVO_D2CRTC_CONTROL);
281 	Write32(OUT, AVIVO_VGA_RENDER_CONTROL, 0);
282 	Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 1);
283 	Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 1);
284 	Write32(OUT, AVIVO_D1CRTC_CONTROL, 0);
285 	Write32(OUT, AVIVO_D2CRTC_CONTROL, 0);
286 	Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 0);
287 	Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 0);
288 	Write32(OUT, AVIVO_D1VGA_CONTROL, 0);
289 	Write32(OUT, AVIVO_D2VGA_CONTROL, 0);
296 	Write32(OUT, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
297 	Write32(OUT, AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
298 	Write32(OUT, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
299 	Write32(OUT, AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
301 	Write32(OUT, AVIVO_VGA_MEMORY_BASE_ADDRESS, gInfo->fb.vramStart);
304 	Write32(OUT, AVIVO_VGA_HDP_CONTROL, gpuState->vgaHdpControl);
308 	Write32(OUT, AVIVO_D1VGA_CONTROL, gpuState->d1vgaControl);
309 	Write32(OUT, AVIVO_D2VGA_CONTROL, gpuState->d2vgaControl);
310 	Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 1);
311 	Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 1);
312 	Write32(OUT, AVIVO_D1CRTC_CONTROL, gpuState->d1crtcControl);
313 	Write32(OUT, AVIVO_D2CRTC_CONTROL, gpuState->d2crtcControl);
314 	Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 0);
315 	Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 0);
316 	Write32(OUT, AVIVO_VGA_RENDER_CONTROL, gpuState->vgaRenderControl);
363 		Write32(OUT, (0x2c14 + j), 0x00000000);
364 		Write32(OUT, (0x2c18 + j), 0x00000000);
365 		Write32(OUT, (0x2c1c + j), 0x00000000);
366 		Write32(OUT, (0x2c20 + j), 0x00000000);
367 		Write32(OUT, (0x2c24 + j), 0x00000000);
369 	Write32(OUT, R600_HDP_REG_COHERENCY_FLUSH_CNTL, 0);
379 	Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
381 	Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
384 	Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
388 	Write32(OUT, R600_MC_VM_FB_LOCATION, tmp);
389 	Write32(OUT, R600_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
390 	Write32(OUT, R600_HDP_NONSURFACE_INFO, (2 << 7));
391 	Write32(OUT, R600_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
394 	//	Write32(OUT, R600_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 22);
395 	//	Write32(OUT, R600_MC_VM_AGP_BOT, gInfo->fb.gartStart >> 22);
396 	//	Write32(OUT, R600_MC_VM_AGP_BASE, gInfo->fb.agpBase >> 22);
398 	Write32(OUT, R600_MC_VM_AGP_BASE, 0);
399 	Write32(OUT, R600_MC_VM_AGP_TOP, 0x0FFFFFFF);
400 	Write32(OUT, R600_MC_VM_AGP_BOT, 0x0FFFFFFF);
408 	Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);
421 		Write32(OUT, (0x2c14 + j), 0x00000000);
422 		Write32(OUT, (0x2c18 + j), 0x00000000);
423 		Write32(OUT, (0x2c1c + j), 0x00000000);
424 		Write32(OUT, (0x2c20 + j), 0x00000000);
425 		Write32(OUT, (0x2c24 + j), 0x00000000);
429 	Read32(OUT, R700_HDP_DEBUG1);
438 	Write32(OUT, AVIVO_VGA_HDP_CONTROL, AVIVO_VGA_MEMORY_DISABLE);
441 	Write32(OUT, R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
443 	Write32(OUT, R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
446 	Write32(OUT, R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
450 	Write32(OUT, R700_MC_VM_FB_LOCATION, tmp);
451 	Write32(OUT, R700_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
452 	Write32(OUT, R700_HDP_NONSURFACE_INFO, (2 << 7));
453 	Write32(OUT, R700_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
456 	//	Write32(OUT, R700_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 22);
457 	//	Write32(OUT, R700_MC_VM_AGP_BOT, gInfo->fb.gartStart >> 22);
458 	//	Write32(OUT, R700_MC_VM_AGP_BASE, gInfo->fb.agpBase >> 22);
460 	Write32(OUT, R700_MC_VM_AGP_BASE, 0);
461 	Write32(OUT, R700_MC_VM_AGP_TOP, 0x0FFFFFFF);
462 	Write32(OUT, R700_MC_VM_AGP_BOT, 0x0FFFFFFF);
470 	Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);
483 		Write32(OUT, (0x2c14 + j), 0x00000000);
484 		Write32(OUT, (0x2c18 + j), 0x00000000);
485 		Write32(OUT, (0x2c1c + j), 0x00000000);
486 		Write32(OUT, (0x2c20 + j), 0x00000000);
487 		Write32(OUT, (0x2c24 + j), 0x00000000);
489 	Write32(OUT, EVERGREEN_HDP_REG_COHERENCY_FLUSH_CNTL, 0);
498 	Write32(OUT, AVIVO_VGA_HDP_CONTROL, AVIVO_VGA_MEMORY_DISABLE);
501 	Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
503 	Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
506 	Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
511 		uint32 tmp = Read32(OUT, EVERGREEN_MC_FUS_VM_FB_OFFSET)
515 		Write32(OUT, EVERGREEN_MC_FUS_VM_FB_OFFSET, tmp);
521 	Write32(OUT, EVERGREEN_MC_VM_FB_LOCATION, tmp);
522 	Write32(OUT, EVERGREEN_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
523 	Write32(OUT, EVERGREEN_HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
524 	Write32(OUT, EVERGREEN_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
527 	//	Write32(OUT, EVERGREEN_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 16);
528 	//	Write32(OUT, EVERGREEN_MC_VM_AGP_BOT, gInfo->fb.gartStart >> 16);
529 	//	Write32(OUT, EVERGREEN_MC_VM_AGP_BASE, gInfo->fb.agpBase >> 22);
531 	Write32(OUT, EVERGREEN_MC_VM_AGP_BASE, 0);
532 	Write32(OUT, EVERGREEN_MC_VM_AGP_TOP, 0x0FFFFFFF);
533 	Write32(OUT, EVERGREEN_MC_VM_AGP_BOT, 0x0FFFFFFF);
541 	Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);
568 		vramBase = Read32(OUT, fbVMLocationReg) & 0xFFFF;
647 	Write32(OUT, GRBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
648 	Read32(OUT, GRBM_SOFT_RESET);
650 	Write32(OUT, GRBM_SOFT_RESET, 0);
659 	Write32(OUT, CP_RB_CNTL, controlScratch);
662 	Write32(OUT, CP_SEM_WAIT_TIMER, 0);
663 	Write32(OUT, CP_RB_WPTR_DELAY, 0);
667 	Write32(OUT, CP_RB_CNTL, controlScratch);
670 	Write32(OUT, CP_RB_RPTR_WR, 0);
671 	Write32(OUT, CP_RB_WPTR, 0);
687 	Write32(OUT, CP_RB_RPTR_ADDR, (ringPointer & 0xfffffffc));
688 	Write32(OUT, CP_RB_RPTR_ADDR_HI, upper_32_bits(ringPointer));
692 	Write32(OUT, CP_RB_CNTL, controlScratch);
713 	Write32(OUT, CP_RB_BASE, commandPointer >> 8);
714 	Write32(OUT, CP_ME_CNTL, 0xff);
715 	Write32(OUT, CP_DEBUG, (1 << 27) | (1 << 28));
723 	uint64 scratchAddr = Read32(OUT, CP_RB_RPTR_ADDR) & 0xFFFFFFFC;
724 	scratchAddr |= ((uint64)Read32(OUT, CP_RB_RPTR_ADDR_HI)) << 32;
729 	Write32(OUT, R600_SCRATCH_ADDR, (uint32)scratchAddr);
731 	Write32(OUT, R600_SCRATCH_UMSK, 0x7);
739 	Write32(OUT, R600_LAST_FRAME_REG, 0);
742 	Write32(OUT, R600_LAST_DISPATCH_REG, 0);
745 	Write32(OUT, R600_LAST_CLEAR_REG, 0);
776 				ssControl = Read32(OUT, EVERGREEN_P1PLL_SS_CNTL);
781 				Write32(OUT, EVERGREEN_P1PLL_SS_CNTL, ssControl);
785 				ssControl = Read32(OUT, EVERGREEN_P2PLL_SS_CNTL);
790 				Write32(OUT, EVERGREEN_P2PLL_SS_CNTL, ssControl);
799 				ssControl = Read32(OUT, AVIVO_P1PLL_INT_SS_CNTL);
804 				Write32(OUT, AVIVO_P1PLL_INT_SS_CNTL, ssControl);
808 				ssControl = Read32(OUT, AVIVO_P2PLL_INT_SS_CNTL);
813 				Write32(OUT, AVIVO_P2PLL_INT_SS_CNTL, ssControl);