Lines Matching refs:regs
40 /*! Populate regs with device dependant register locations */
42 init_registers(register_info* regs, uint8 crtcID)
44 memset(regs, 0, sizeof(register_info));
55 regs->vgaControl = AVIVO_D1VGA_CONTROL;
59 regs->vgaControl = AVIVO_D2VGA_CONTROL;
63 regs->vgaControl = EVERGREEN_D3VGA_CONTROL;
67 regs->vgaControl = EVERGREEN_D4VGA_CONTROL;
71 regs->vgaControl = EVERGREEN_D5VGA_CONTROL;
75 regs->vgaControl = EVERGREEN_D6VGA_CONTROL;
83 regs->crtcOffset = offset;
85 regs->grphEnable = EVERGREEN_GRPH_ENABLE + offset;
86 regs->grphControl = EVERGREEN_GRPH_CONTROL + offset;
87 regs->grphSwapControl = EVERGREEN_GRPH_SWAP_CONTROL + offset;
89 regs->grphPrimarySurfaceAddr
91 regs->grphSecondarySurfaceAddr
93 regs->grphPrimarySurfaceAddrHigh
95 regs->grphSecondarySurfaceAddrHigh
98 regs->grphPitch = EVERGREEN_GRPH_PITCH + offset;
99 regs->grphSurfaceOffsetX
101 regs->grphSurfaceOffsetY
103 regs->grphXStart = EVERGREEN_GRPH_X_START + offset;
104 regs->grphYStart = EVERGREEN_GRPH_Y_START + offset;
105 regs->grphXEnd = EVERGREEN_GRPH_X_END + offset;
106 regs->grphYEnd = EVERGREEN_GRPH_Y_END + offset;
107 regs->modeDesktopHeight = EVERGREEN_DESKTOP_HEIGHT + offset;
108 regs->modeDataFormat = EVERGREEN_DATA_FORMAT + offset;
109 regs->viewportStart = EVERGREEN_VIEWPORT_START + offset;
110 regs->viewportSize = EVERGREEN_VIEWPORT_SIZE + offset;
119 regs->vgaControl = AVIVO_D1VGA_CONTROL;
120 regs->grphPrimarySurfaceAddrHigh
125 regs->vgaControl = AVIVO_D2VGA_CONTROL;
126 regs->grphPrimarySurfaceAddrHigh
135 regs->crtcOffset = offset;
137 regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset;
138 regs->grphControl = AVIVO_D1GRPH_CONTROL + offset;
139 regs->grphSwapControl = AVIVO_D1GRPH_SWAP_CNTL + offset;
141 regs->grphPrimarySurfaceAddr
143 regs->grphSecondarySurfaceAddr
146 regs->grphPitch = AVIVO_D1GRPH_PITCH + offset;
147 regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset;
148 regs->grphSurfaceOffsetY = AVIVO_D1GRPH_SURFACE_OFFSET_Y + offset;
149 regs->grphXStart = AVIVO_D1GRPH_X_START + offset;
150 regs->grphYStart = AVIVO_D1GRPH_Y_START + offset;
151 regs->grphXEnd = AVIVO_D1GRPH_X_END + offset;
152 regs->grphYEnd = AVIVO_D1GRPH_Y_END + offset;
154 regs->modeDesktopHeight = AVIVO_D1MODE_DESKTOP_HEIGHT + offset;
155 regs->modeDataFormat = AVIVO_D1MODE_DATA_FORMAT + offset;
156 regs->viewportStart = AVIVO_D1MODE_VIEWPORT_START + offset;
157 regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset;
166 regs->vgaControl = AVIVO_D1VGA_CONTROL;
170 regs->vgaControl = AVIVO_D2VGA_CONTROL;
178 regs->crtcOffset = offset;
180 regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset;
181 regs->grphControl = AVIVO_D1GRPH_CONTROL + offset;
182 regs->grphSwapControl = AVIVO_D1GRPH_SWAP_CNTL + offset;
184 regs->grphPrimarySurfaceAddr
186 regs->grphSecondarySurfaceAddr
190 regs->grphPrimarySurfaceAddrHigh = 0xDEAD;
191 regs->grphSecondarySurfaceAddrHigh = 0xDEAD;
193 regs->grphPitch = AVIVO_D1GRPH_PITCH + offset;
194 regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset;
195 regs->grphSurfaceOffsetY = AVIVO_D1GRPH_SURFACE_OFFSET_Y + offset;
196 regs->grphXStart = AVIVO_D1GRPH_X_START + offset;
197 regs->grphYStart = AVIVO_D1GRPH_Y_START + offset;
198 regs->grphXEnd = AVIVO_D1GRPH_X_END + offset;
199 regs->grphYEnd = AVIVO_D1GRPH_Y_END + offset;
201 regs->modeDesktopHeight = AVIVO_D1MODE_DESKTOP_HEIGHT + offset;
202 regs->modeDataFormat = AVIVO_D1MODE_DATA_FORMAT + offset;
203 regs->viewportStart = AVIVO_D1MODE_VIEWPORT_START + offset;
204 regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset;
370 init_registers(gDisplay[displayIndex]->regs, displayIndex);
597 register_info* regs = gDisplay[crtcID]->regs;
606 Write32(OUT, NI_INPUT_CSC_CONTROL + regs->crtcOffset,
609 Write32(OUT, NI_PRESCALE_GRPH_CONTROL + regs->crtcOffset,
611 Write32(OUT, NI_PRESCALE_OVL_CONTROL + regs->crtcOffset,
613 Write32(OUT, NI_INPUT_GAMMA_CONTROL + regs->crtcOffset,
618 Write32(OUT, EVERGREEN_DC_LUT_CONTROL + regs->crtcOffset, 0);
620 Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + regs->crtcOffset, 0);
621 Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + regs->crtcOffset, 0);
622 Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_RED + regs->crtcOffset, 0);
624 Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff);
625 Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff);
626 Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff);
633 Write32(OUT, EVERGREEN_DC_LUT_30_COLOR + regs->crtcOffset,
638 Write32(OUT, NI_DEGAMMA_CONTROL + regs->crtcOffset,
643 Write32(OUT, NI_GAMUT_REMAP_CONTROL + regs->crtcOffset,
646 Write32(OUT, NI_REGAMMA_CONTROL + regs->crtcOffset,
649 Write32(OUT, NI_OUTPUT_CSC_CONTROL + regs->crtcOffset,
653 Write32(OUT, 0x6940 + regs->crtcOffset, 0);
662 register_info* regs = gDisplay[crtcID]->regs;
670 Write32(OUT, AVIVO_DC_LUTA_CONTROL + regs->crtcOffset, 0);
672 Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + regs->crtcOffset, 0);
673 Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + regs->crtcOffset, 0);
674 Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_RED + regs->crtcOffset, 0);
676 Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff);
677 Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff);
678 Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff);
690 Write32(OUT, AVIVO_D1GRPH_LUT_SEL + regs->crtcOffset, crtcID);
698 register_info* regs = gDisplay[crtcID]->regs;
802 Write32(OUT, regs->vgaControl, 0);
812 Write32(OUT, regs->grphPrimarySurfaceAddrHigh,
814 Write32(OUT, regs->grphSecondarySurfaceAddrHigh,
821 Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddress & 0xFFFFFFFF));
822 Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddress & 0xFFFFFFFF));
825 Write32(CRT, regs->grphControl, fbFormat);
826 Write32(CRT, regs->grphSwapControl, fbSwap);
855 Write32(CRT, regs->grphSurfaceOffsetX, 0);
856 Write32(CRT, regs->grphSurfaceOffsetY, 0);
857 Write32(CRT, regs->grphXStart, 0);
858 Write32(CRT, regs->grphYStart, 0);
859 Write32(CRT, regs->grphXEnd, mode->virtual_width);
860 Write32(CRT, regs->grphYEnd, mode->virtual_height);
861 Write32(CRT, regs->grphPitch, widthAligned);
863 Write32(CRT, regs->grphEnable, 1);
866 Write32(CRT, regs->modeDesktopHeight, mode->virtual_height);
871 Write32(CRT, regs->viewportStart, 0);
872 Write32(CRT, regs->viewportSize,
878 = Read32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset);
880 Write32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);
882 Write32(OUT, EVERGREEN_MASTER_UPDATE_MODE + regs->crtcOffset, 0);
886 uint32 tmp = Read32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset);
888 Write32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);
890 Write32(OUT, AVIVO_D1MODE_MASTER_UPDATE_MODE + regs->crtcOffset, 0);