Lines Matching refs:pll
998 display_crtc_ss(pll_info* pll, int command)
1004 if (pll->ssPercentage == 0) {
1008 if ((pll->ssType & ATOM_EXTERNAL_SS_MASK) != 0) {
1013 if (pll_usage_count(pll->id) > 1) {
1036 = pll->ssType & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
1037 switch (pll->id) {
1053 args.v3.usSpreadSpectrumAmount = B_HOST_TO_LENDIAN_INT16(pll->ssAmount);
1054 args.v3.usSpreadSpectrumStep = B_HOST_TO_LENDIAN_INT16(pll->ssStep);
1058 = B_HOST_TO_LENDIAN_INT16(pll->ssPercentage);
1060 = pll->ssType & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
1061 switch (pll->id) {
1077 args.v2.usSpreadSpectrumAmount = B_HOST_TO_LENDIAN_INT16(pll->ssAmount);
1078 args.v2.usSpreadSpectrumStep = B_HOST_TO_LENDIAN_INT16(pll->ssStep);
1082 = B_HOST_TO_LENDIAN_INT16(pll->ssPercentage);
1084 = pll->ssType & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
1085 args.v1.ucSpreadSpectrumStep = pll->ssStep;
1086 args.v1.ucSpreadSpectrumDelay = pll->ssDelay;
1087 args.v1.ucSpreadSpectrumRange = pll->ssRange;
1088 args.v1.ucPpll = pll->id;
1092 radeon_gpu_ss_control(pll, false);
1096 = B_HOST_TO_LENDIAN_INT16(pll->ssPercentage);
1098 = pll->ssType & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
1099 args.lvds_ss_2.ucSpreadSpectrumStep = pll->ssStep;
1100 args.lvds_ss_2.ucSpreadSpectrumDelay = pll->ssDelay;
1101 args.lvds_ss_2.ucSpreadSpectrumRange = pll->ssRange;