accelerants/radeon_hd/display.cpp

606 		Write32(OUT, NI_INPUT_CSC_CONTROL + regs->crtcOffset,
609 		Write32(OUT, NI_PRESCALE_GRPH_CONTROL + regs->crtcOffset,
611 		Write32(OUT, NI_PRESCALE_OVL_CONTROL + regs->crtcOffset,
613 		Write32(OUT, NI_INPUT_GAMMA_CONTROL + regs->crtcOffset,
618 	Write32(OUT, EVERGREEN_DC_LUT_CONTROL + regs->crtcOffset, 0);
620 	Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + regs->crtcOffset, 0);
621 	Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + regs->crtcOffset, 0);
622 	Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_RED + regs->crtcOffset, 0);
624 	Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff);
625 	Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff);
626 	Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff);
628 	Write32(OUT, EVERGREEN_DC_LUT_RW_MODE, 0);
629 	Write32(OUT, EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007);
631 	Write32(OUT, EVERGREEN_DC_LUT_RW_INDEX, 0);
633 		Write32(OUT, EVERGREEN_DC_LUT_30_COLOR + regs->crtcOffset,
638 		Write32(OUT, NI_DEGAMMA_CONTROL + regs->crtcOffset,
643 		Write32(OUT, NI_GAMUT_REMAP_CONTROL + regs->crtcOffset,
646 		Write32(OUT, NI_REGAMMA_CONTROL + regs->crtcOffset,
649 		Write32(OUT, NI_OUTPUT_CSC_CONTROL + regs->crtcOffset,
653 		Write32(OUT, 0x6940 + regs->crtcOffset, 0);
670 	Write32(OUT, AVIVO_DC_LUTA_CONTROL + regs->crtcOffset, 0);
672 	Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + regs->crtcOffset, 0);
673 	Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + regs->crtcOffset, 0);
674 	Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_RED + regs->crtcOffset, 0);
676 	Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff);
677 	Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff);
678 	Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff);
680 	Write32(OUT, AVIVO_DC_LUT_RW_SELECT, crtcID);
681 	Write32(OUT, AVIVO_DC_LUT_RW_MODE, 0);
682 	Write32(OUT, AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
684 	Write32(OUT, AVIVO_DC_LUT_RW_INDEX, 0);
686 		Write32(OUT, AVIVO_DC_LUT_30_COLOR,
690 	Write32(OUT, AVIVO_D1GRPH_LUT_SEL + regs->crtcOffset, crtcID);
802 	Write32(OUT, regs->vgaControl, 0);
812 		Write32(OUT, regs->grphPrimarySurfaceAddrHigh,
814 		Write32(OUT, regs->grphSecondarySurfaceAddrHigh,
821 	Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddress & 0xFFFFFFFF));
822 	Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddress & 0xFFFFFFFF));
878 			= Read32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset);
880 		Write32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);
882 		Write32(OUT, EVERGREEN_MASTER_UPDATE_MODE + regs->crtcOffset, 0);
886 		uint32 tmp = Read32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset);
888 		Write32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);
890 		Write32(OUT, AVIVO_D1MODE_MASTER_UPDATE_MODE + regs->crtcOffset, 0);