accelerants/radeon/set_mode.h

208 void Radeon_CalcCRTCRegisters( accelerator_info *ai, crtc_info *crtc,
210 void Radeon_ProgramCRTCRegisters( accelerator_info *ai, int crtc_idx,
217 void Radeon_ProgramPLL( accelerator_info *ai, int crtc_idx, pll_regs *values );
233 void Radeon_ReadRMXRegisters( accelerator_info *ai, fp_regs *values );
235 void Radeon_ProgramRMXRegisters( accelerator_info *ai, fp_regs *values );
237 void Radeon_ReadFPRegisters( accelerator_info *ai, fp_regs *values );
238 void Radeon_CalcFPRegisters( accelerator_info *ai, crtc_info *crtc,
240 void Radeon_ProgramFPRegisters( accelerator_info *ai, crtc_info *crtc,
246 	accelerator_info *ai, routing_regs *values );
248 	accelerator_info *ai, const impactv_params *tv_parameters, routing_regs *values );
250 	accelerator_info *ai, routing_regs *values );
252 	accelerator_info *ai, int whished_num_heads, bool use_laptop_panel );
258 	accelerator_info *ai, uint16 addr, uint32 value );
260 	accelerator_info *ai, uint16 addr );
267 	accelerator_info *ai, display_mode *mode,
271 	accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values, bool internal_encoder );
273 	accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values );
277 void Radeon_TheatreProgramTVRegisters( accelerator_info *ai, impactv_regs *values );
278 void Radeon_TheatreReadTVRegisters( accelerator_info *ai, impactv_regs *values );
279 uint32 Radeon_TheatreReadFIFO( accelerator_info *ai, uint16 addr );
280 void Radeon_TheatreWriteFIFO( accelerator_info *ai, uint16 addr, uint32 value );
283 void Radeon_InternalTVOutProgramRegisters( accelerator_info *ai, impactv_regs *values );
284 void Radeon_InternalTVOutReadRegisters( accelerator_info *ai, impactv_regs *values );