accelerants/radeon/pll.c

47 // pll - info about PLL
52 	const pll_info *pll, uint32 freq, uint fixed_post_div, pll_dividers *dividers )
96 			pll->post_divs[max_post_div_idx].divider != 0;
103 			pll->post_divs[min_post_div_idx].divider != fixed_post_div;
113 	for( extra_post_div_idx = 0; pll->extra_post_divs[extra_post_div_idx].divider != 0; ++extra_post_div_idx ) {
117 				pll->post_divs[post_div_idx].divider
118 				* pll->extra_post_divs[extra_post_div_idx].divider;
127 			if( vco < pll->vco_min || vco > pll->vco_max )
134 			for( ref_div = pll->min_ref_div; ref_div <= pll->max_ref_div; ++ref_div ) {
139 				uint32 pll_in = pll->ref_freq / ref_div;
141 				if( pll_in < pll->pll_in_min || pll_in > pll->pll_in_max )
148 					pll->ref_freq * 10000 * pll->extra_feedback_div);
150 				if( feedback_div < pll->min_feedback_div ||
151 					feedback_div > pll->max_feedback_div )
156 					(int64)pll->ref_freq * 10000 * feedback_div * pll->extra_feedback_div,
162 				vco_dev = abs( (int32)vco - (int32)(pll->best_vco) );
169 				if( (pll->best_vco == 0 && error < best_error) ||
170 					(pll->best_vco != 0 &&
187 	dividers->post_code = pll->post_divs[best_post_div_idx].code;
188 	dividers->post = pll->post_divs[best_post_div_idx].divider;
189 	dividers->extra_post_code = pll->post_divs[best_extra_post_div_idx].code;
190 	dividers->extra_post = pll->post_divs[best_extra_post_div_idx].divider;
211 	const pll_info *pll,
257 					Radeon_CalcPLLDividers( pll, crt_freq, fixed_post_div, dividers );
348 void Radeon_GetTVPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
351 	pll->post_divs = tv_post_divs;
352 	pll->extra_post_divs = internal_encoder ? extra_post_divs : external_extra_post_divs;
353 	pll->ref_freq = general_pll->ref_freq;
354 	pll->vco_min = 10000;
355 	pll->vco_max = 25000;
357 	pll->min_ref_div = 4;
358 	pll->max_ref_div = 0x3ff;
362 	pll->pll_in_min = 20;//40;
364 	pll->pll_in_max = 100;
365 	pll->extra_feedback_div = 1;
366 	pll->min_feedback_div = 4;
367 	pll->max_feedback_div = 0x7ff;
368 	pll->best_vco = 21000;
373 void Radeon_GetTVCRTPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
376 	pll->post_divs = post_divs;
377 	pll->extra_post_divs = extra_post_divs;
378 	pll->ref_freq = general_pll->ref_freq;
382 	/*pll->vco_min = general_pll->min_pll_freq;
383 	pll->vco_max = general_pll->max_pll_freq;*/
390 	pll->vco_min = 4000;
391 	pll->vco_max = general_pll->max_pll_freq;
394 	pll->min_ref_div = 2;
395 	pll->max_ref_div = 0x3ff;
396 	pll->pll_in_min = 20;
397 	pll->pll_in_max = 100;
398 	pll->extra_feedback_div = 1;
399 	pll->min_feedback_div = 4;
400 	pll->max_feedback_div = 0x7ff;
401 	pll->best_vco = internal_tv_encoder ? 17500 : 21000;
410 	pll_info pll;
412 	pll.post_divs = post_divs;
413 	pll.extra_post_divs = extra_post_divs;
414 	pll.ref_freq = general_pll->ref_freq;
415 	pll.vco_min = general_pll->min_pll_freq;
416 	pll.vco_max = general_pll->max_pll_freq;
417 	pll.min_ref_div = 2;
418 	pll.max_ref_div = 0x3ff;
419 	pll.pll_in_min = 40;
420 	pll.pll_in_max = 100;
421 	pll.extra_feedback_div = 1;
422 	pll.min_feedback_div = 4;
423 	pll.max_feedback_div = 0x7ff;
424 	pll.best_vco = 0;
428 	Radeon_CalcPLLDividers( &pll, mode->timing.pixel_clock, 0, dividers );