accelerants/radeon/monitor_routing.c

25 // read regs needed for display device routing
29 	vuint8 *regs = ai->regs;
31 	values->dac_cntl = INREG( regs, RADEON_DAC_CNTL );
32 	values->dac_cntl2 = INREG( regs, RADEON_DAC_CNTL2 );
33 	values->crtc_ext_cntl = INREG( regs, RADEON_CRTC_EXT_CNTL );
34 	values->crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );
35 	values->disp_output_cntl = INREG( regs, RADEON_DISP_OUTPUT_CNTL );
36 	values->pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL );
37 	values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL );
47 		values->disp_hw_debug = INREG( regs, RADEON_DISP_HW_DEBUG );
51 		values->disp_tv_out_cntl = INREG( regs, RADEON_DISP_TV_OUT_CNTL );
59 		values->gpiopad_a = INREG( regs, RADEON_GPIOPAD_A );
68 		values->tv_dac_cntl = INREG( regs, RADEON_TV_DAC_CNTL );
72 		values->tv_master_cntl = INREG( regs, RADEON_TV_MASTER_CNTL );
74 	values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );
75 	values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
422 	vuint8 *regs = ai->regs;
424 	OUTREG( regs, RADEON_DAC_CNTL, values->dac_cntl );
425 	OUTREG( regs, RADEON_DAC_CNTL2, values->dac_cntl2 );
426 	OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc2_gen_cntl,
428 	OUTREG( regs, RADEON_DISP_OUTPUT_CNTL, values->disp_output_cntl );
438 		OUTREG( regs, RADEON_DISP_HW_DEBUG, values->disp_hw_debug );
442 		OUTREG( regs, RADEON_DISP_TV_OUT_CNTL, values->disp_tv_out_cntl );
450 		OUTREGP( regs, RADEON_GPIOPAD_A, values->gpiopad_a, ~1 );
462 			OUTREG( regs, RADEON_TV_DAC_CNTL, values->tv_dac_cntl );
466 		OUTREG( regs, RADEON_TV_MASTER_CNTL, values->tv_master_cntl );
468 	OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, ~(
481 	OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
485 		Radeon_OUTPLLP( ai->regs, ai->si->asic,
491 		Radeon_OUTPLLP( ai->regs, ai->si->asic,
496 	Radeon_OUTPLLP( ai->regs, ai->si->asic,
504 		crtc_gen_cntl = INREG( regs, RADEON_CRTC_GEN_CNTL );
513 		OUTREGP( regs, RADEON_CRTC_GEN_CNTL, crtc_gen_cntl,
521 		crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );
530 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl,
535 	OUTREGP( regs, RADEON_CRTC_EXT_CNTL, values->crtc_ext_cntl,