accelerants/radeon/monitor_detection.c

41 	uint32 value;
43 	value = INREG(regs, info->port);
44 	*clk = (value >> RADEON_GPIO_Y_SHIFT_1) & 1;
45 	*data = (value >> RADEON_GPIO_Y_SHIFT_0) & 1;
57 	uint32 value;
59 	value = INREG(regs, info->port);
60 	value &= ~(RADEON_GPIO_A_1 | RADEON_GPIO_A_0);
61 	value &= ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1);
62 	value |= ((1-clk) << RADEON_GPIO_EN_SHIFT_1)
65 	OUTREG(regs, info->port, value);
105 	uint32 old_crtc_ext_cntl, old_dac_ext_cntl, old_dac_cntl, value;
111 	value = old_crtc_ext_cntl | RADEON_CRTC_CRT_ON;
112 	OUTREG(regs, RADEON_CRTC_EXT_CNTL, value);
118 	value = RADEON_DAC_FORCE_BLANK_OFF_EN | RADEON_DAC_FORCE_DATA_EN
121 	OUTREG(regs, RADEON_DAC_EXT_CNTL, value);
126 	value = old_dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
127 	value |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
128 	OUTREG(regs, RADEON_DAC_CNTL, value);
155 	vuint32 old_vclk_ecp_cntl, value;
162 	value = old_vclk_ecp_cntl
164 	Radeon_OUTPLL(ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL, value);
181 	uint32 old_crtc2_gen_cntl, old_tv_dac_cntl, old_dac_cntl2, value;
184 	// enable CRTC2, setting 8 bpp (we just pick any valid value)
187 	value = old_crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
188 	value |= RADEON_CRTC2_CRT2_ON | (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
189 	OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value);
194 	value = RADEON_TV_DAC_CNTL_NBLANK | RADEON_TV_DAC_CNTL_NHOLD
196 	OUTREG(regs, RADEON_TV_DAC_CNTL, value);
199 	value = RADEON_DAC2_FORCE_BLANK_OFF_EN | RADEON_DAC2_FORCE_DATA_EN
202 	OUTREG(regs, RADEON_DAC_EXT_CNTL, value);
208 	value = old_dac_cntl2 | RADEON_DAC2_CLK_SEL_CRT | RADEON_DAC2_CMP_EN;
209 	OUTREG(regs, RADEON_DAC_CNTL2, value);
232 	uint32 old_crtc2_gen_cntl, old_tv_dac_cntl, old_dac_cntl2, value;
248 	value = old_crtc2_gen_cntl;
249 	value &= ~RADEON_CRTC2_PIX_WIDTH_MASK;
250 	value |= (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT) | RADEON_CRTC2_CRT2_ON
252 	OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value);
335 	uint32 value, old_dac_cntl2, old_crtc_ext_cntl, old_crtc2_gen_cntl;
346 	value = old_dac_cntl2 & ~RADEON_DAC2_CLK_SEL_CRT;
347 	OUTREG(regs, RADEON_DAC_CNTL2, value);
354 	value = old_tv_master_cntl | RADEON_TV_MASTER_CNTL_TV_ON;
355 	value &= ~(
361 	value |=
364 	OUTREG(regs, RADEON_TV_MASTER_CNTL, value);
371 	value =
376 	OUTREG(regs, RADEON_TV_DAC_CNTL, value);
381 	value =
387 	OUTREG(regs, RADEON_TV_PRE_DAC_MUX_CNTL, value);
393 	value = INREG(regs, RADEON_TV_DAC_CNTL);
394 	if ((value & RADEON_TV_DAC_CNTL_GDACDET) != 0) {
399 	if ((value & RADEON_TV_DAC_CNTL_BDACDET) != 0) {