Lines Matching refs:offsetof
33 { RADEON_TV_MASTER_CNTL, offsetof( impactv_regs, tv_master_cntl ) },
34 { RADEON_TV_HRESTART, offsetof( impactv_regs, tv_hrestart ) },
35 { RADEON_TV_VRESTART, offsetof( impactv_regs, tv_vrestart ) },
36 { RADEON_TV_FRESTART, offsetof( impactv_regs, tv_frestart ) },
37 { RADEON_TV_FTOTAL, offsetof( impactv_regs, tv_ftotal ) },
43 { RADEON_TV_PLL_CNTL, offsetof( impactv_regs, tv_tv_pll_cntl ) },
44 { RADEON_TV_PLL_CNTL1, offsetof( impactv_regs, tv_pll_cntl1 ) },
45 { RADEON_TV_PLL_FINE_CNTL, offsetof( impactv_regs, tv_pll_fine_cntl ) },
51 { RADEON_TV_HTOTAL, offsetof( impactv_regs, tv_htotal ) },
52 { RADEON_TV_HDISP, offsetof( impactv_regs, tv_hdisp ) },
53 { RADEON_TV_HSTART, offsetof( impactv_regs, tv_hstart ) },
54 { RADEON_TV_VTOTAL, offsetof( impactv_regs, tv_vtotal ) },
55 { RADEON_TV_VDISP, offsetof( impactv_regs, tv_vdisp ) },
57 { RADEON_TV_TIMING_CNTL, offsetof( impactv_regs, tv_timing_cntl ) },
59 { RADEON_TV_VSCALER_CNTL1, offsetof( impactv_regs, tv_vscaler_cntl1 ) },
60 { RADEON_TV_VSCALER_CNTL2, offsetof( impactv_regs, tv_vscaler_cntl2 ) },
62 { RADEON_TV_Y_SAW_TOOTH_CNTL, offsetof( impactv_regs, tv_y_saw_tooth_cntl ) },
63 { RADEON_TV_Y_RISE_CNTL, offsetof( impactv_regs, tv_y_rise_cntl ) },
64 { RADEON_TV_Y_FALL_CNTL, offsetof( impactv_regs, tv_y_fall_cntl ) },
66 { RADEON_TV_MODULATOR_CNTL1, offsetof( impactv_regs, tv_modulator_cntl1 ) },
67 { RADEON_TV_MODULATOR_CNTL2, offsetof( impactv_regs, tv_modulator_cntl2 ) },
68 { RADEON_TV_RGB_CNTL, offsetof( impactv_regs, tv_rgb_cntl ) },
69 { RADEON_TV_UV_ADR, offsetof( impactv_regs, tv_uv_adr ) },
70 { RADEON_TV_PRE_DAC_MUX_CNTL, offsetof( impactv_regs, tv_pre_dac_mux_cntl ) },
71 { RADEON_TV_CRC_CNTL, offsetof( impactv_regs, tv_crc_cntl ) },
77 { RADEON_TV_GAIN_LIMIT_SETTINGS, offsetof( impactv_regs, tv_gain_limit_settings ) },
78 { RADEON_TV_LINEAR_GAIN_SETTINGS, offsetof( impactv_regs, tv_linear_gain_settings ) },
79 { RADEON_TV_UPSAMP_AND_GAIN_CNTL, offsetof( impactv_regs, tv_upsamp_and_gain_cntl ) },
81 { RADEON_TV_DAC_CNTL, offsetof( impactv_regs, tv_dac_cntl ) },
82 { RADEON_TV_MASTER_CNTL, offsetof( impactv_regs, tv_master_cntl ) },