accelerants/radeon/internal_tv_out.c

91 	accelerator_info *ai, impactv_regs *values, const register_mapping *mapping )
97 			*(uint32 *)((char *)(values) + mapping->offset) );*/
99 		OUTREG( regs, mapping->address, *(uint32 *)((char *)(values) + mapping->offset) );
108 	accelerator_info *ai, impactv_regs *values, const register_mapping *mapping )
112 			*(uint32 *)((char *)(values) + mapping->offset) );*/
115 			mapping->address, *(uint32 *)((char *)(values) + mapping->offset) );
188 	accelerator_info *ai, impactv_regs *values )
190 	uint32 orig_tv_master_cntl = values->tv_master_cntl;
196 	values->tv_master_cntl |=
205 	writeMMIORegList( ai, values, intern_reg_mapping_before_pll );
206 	writePLLRegList( ai, values, intern_reg_mapping_pll );
207 	writeMMIORegList( ai, values, intern_reg_mapping_after_pll );
219 	Radeon_ImpacTVwriteHorTimingTable( ai, Radeon_InternalTVOutWriteFIFO, values, true );
220 	Radeon_ImpacTVwriteVertTimingTable( ai, Radeon_InternalTVOutWriteFIFO, values );
224 	values->tv_master_cntl = orig_tv_master_cntl;
225 	writeMMIORegList( ai, values, intern_reg_mapping_finish );
231 	accelerator_info *ai, impactv_regs *values, const register_mapping *mapping )
236 		*(uint32 *)((char *)(values) + mapping->offset) =
240 			*(uint32 *)((char *)(values) + mapping->offset) );*/
249 	accelerator_info *ai, impactv_regs *values, const register_mapping *mapping )
252 		*(uint32 *)((char *)(values) + mapping->offset) =
256 			*(uint32 *)((char *)(values) + mapping->offset) );*/
265 	accelerator_info *ai, impactv_regs *values )
267 	readMMIORegList( ai, values, intern_reg_mapping_before_pll );
268 	readPLLRegList( ai, values, intern_reg_mapping_pll );
269 	readMMIORegList( ai, values, intern_reg_mapping_after_pll );
270 	readMMIORegList( ai, values, intern_reg_mapping_finish );