accelerants/radeon/impactv.c

31 	impactv_params *params, const display_mode *mode,
46 	tmp_uv_accum_sum = params->uv_accum_init << (TV_UV_INC_FIX_SHIFT - TV_UV_INIT_FIX_SHIFT);
60 			uv_accum_int = ((uv_accum_frac + params->uv_inc) >> TV_UV_INC_FIX_SHIFT) - 1;
61 			uv_accum_frac = (uv_accum_frac + params->uv_inc) & (TV_UV_INC_FIX_SCALE - 1);
78 	//params->tv_clocks_to_active = 0;
79 	time_to_active = params->tv_clocks_to_active + 3;
82 		time_to_active, params->crt_dividers.freq, params->tv_dividers.freq );
87 			(int64)time_to_active * params->crt_dividers.freq / params->tv_dividers.freq
88 			- (int64)h_blank * params->crt_dividers.freq / params->tv_dividers.freq / 2)
108 	params->f_restart = (first_num / (mode->timing.v_total * mode->timing.h_total)) % f_total;
110 	params->v_restart = (first_num / mode->timing.h_total) % mode->timing.v_total;
112 	params->h_restart = first_num;
114 	/*params->v_restart = 623;
115 	params->h_restart = 580;*/
118 		params->f_restart, params->v_restart, params->h_restart );
142 	impactv_params *params )
149 	lower_border = ((params->uv_inc + TV_UV_INC_FIX_SCALE - 1) >> TV_UV_INC_FIX_SHIFT);
150 	upper_border = ((2 * params->uv_inc) >> TV_UV_INC_FIX_SHIFT);
166 	params->y_saw_tooth_slope = y_saw_tooth_slope[i] * (TV_SAW_FILTER_FIX_SCALE / 8);
167 	params->y_saw_tooth_amp = ((uint32)params->y_saw_tooth_slope * params->uv_inc) >> TV_UV_INC_FIX_SHIFT;
168 	params->y_fall_accum_init = ((uint32)params->y_saw_tooth_slope * params->uv_accum_init) >> TV_UV_INIT_FIX_SHIFT;
171 		(flicker_removal << 16) - ((int32)params->uv_inc << (16 - TV_UV_INC_FIX_SHIFT)),
172 		((int32)params->uv_accum_init << (16 - TV_UV_INIT_FIX_SHIFT)) );
174 	if( (flicker_removal << 16) - ((int32)params->uv_inc << (16 - TV_UV_INC_FIX_SHIFT))
175 		< ((int32)params->uv_accum_init << (16 - TV_UV_INIT_FIX_SHIFT)))
177 		params->y_rise_accum_init =
178 			(((flicker_removal << TV_UV_INIT_FIX_SHIFT) - params->uv_accum_init) *
179 			params->y_saw_tooth_slope) >> TV_UV_INIT_FIX_SHIFT;
181 		params->y_rise_accum_init =
182 			(((flicker_removal << TV_UV_INIT_FIX_SHIFT) - params->uv_accum_init - params->y_accum_init) *
183 			params->y_saw_tooth_slope) >> TV_UV_INIT_FIX_SHIFT;
186 	params->y_coeff_enable = y_coeff_enable[i];
187 	params->y_coeff_value = y_coeff_value[i] * TV_Y_COEFF_FIX_SCALE / 8;
324 	const general_pll_info *general_pll, impactv_params *params,
338 	params->mode888 = true;
339 	params->timing = *tv_timing;
342 	Radeon_CalcPLLDividers( &tv_pll, tv_timing->freq, 0, &params->tv_dividers );
357 		internal_encoder ? 0/*6*/ : 0, 2 + params->mode888,
358 		&params->crt_dividers, tweaked_mode );
376 	params->tv_clocks_to_active = (uint32)lines_before_active * tv_timing->h_total + start_line;
381 	params->uv_accum_init = 0x10;
384 	params->y_accum_init = 0;
387 	params->uv_inc = (tweaked_mode->timing.v_total << TV_UV_INC_FIX_SHIFT)
390 	SHOW_FLOW( 3, "uv_inc=%d", params->uv_inc );
392 	params->h_inc =
396 	Radeon_CalcImpacTVRestart( params, tweaked_mode,
398 	Radeon_CalcImpacTVFlickerFixer( params );
418 	impactv_params *params, impactv_regs *values, int crtc_idx,
421 	const tv_timing *timing = &params->timing;
436 		params->uv_inc;
450 		params->y_saw_tooth_amp |
451 		(params->y_saw_tooth_slope << RADEON_TV_Y_SAW_TOOTH_CNTL_SLOPE_SHIFT);
454 		params->y_fall_accum_init |
456 		(params->y_coeff_enable ? RADEON_TV_Y_FALL_CNTL_Y_COEFF_EN : 0) |
457 		(params->y_coeff_value << RADEON_TV_Y_FALL_CNTL_Y_COEFF_VALUE_SHIFT);
460 		params->y_rise_accum_init |
466 		(params->uv_accum_init << RADEON_TV_VSCALER_CNTL2_UV_ACCUM_INIT_SHIFT);
476 	values->tv_hrestart = params->h_restart;
477 	values->tv_vrestart = params->v_restart;
478 	values->tv_frestart = params->f_restart;
481 		(params->tv_dividers.ref & RADEON_TV_PLL_CNTL_TV_M0_LO_MASK) |
482 		((params->tv_dividers.feedback & RADEON_TV_PLL_CNTL_TV_N0_LO_MASK)
484 		((params->tv_dividers.ref >> RADEON_TV_PLL_CNTL_TV_M0_LO_BITS)
486 		((params->tv_dividers.feedback >> RADEON_TV_PLL_CNTL_TV_N0_LO_BITS)
490 		(params->tv_dividers.post << RADEON_TV_PLL_CNTL_TV_P_SHIFT); //|
494 		(params->crt_dividers.ref & RADEON_TV_CRT_PLL_CNTL_M0_LO_MASK) |
495 		((params->crt_dividers.feedback & RADEON_TV_CRT_PLL_CNTL_N0_LO_MASK)
497 		((params->crt_dividers.ref >> RADEON_TV_CRT_PLL_CNTL_M0_LO_BITS)
499 		((params->crt_dividers.feedback >> RADEON_TV_CRT_PLL_CNTL_N0_LO_BITS)
501 		(params->crt_dividers.extra_post == 2 ? RADEON_TV_CRT_PLL_CNTL_CLKBY2 : 0);
508 		((/*params->crt_dividers.post_code - 1*/0) << RADEON_TV_CLOCK_SEL_CNTL_BYTCLK_SHIFT) |
520 		values->tv_hdisp + 1 - params->mode888 + 12;
528 		params->h_inc;
684 		values->tv_rgb_cntl = params->mode888;