accelerants/radeon/flat_panel.c

23 	vuint8 *regs = ai->regs;
25 	values->fp_horz_stretch = INREG( regs, RADEON_FP_HORZ_STRETCH );
26 	values->fp_vert_stretch = INREG( regs, RADEON_FP_VERT_STRETCH );
110 	vuint8 *regs = ai->regs;
112 	OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch );
113 	OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch );
120 	vuint8 *regs = ai->regs;
122 	values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );
123 	values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
124 	values->lvds_gen_cntl = INREG( regs, RADEON_LVDS_GEN_CNTL );
125 	values->tmds_pll_cntl = INREG( regs, RADEON_TMDS_PLL_CNTL );
126 	values->tmds_trans_cntl = INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL );
127 	values->fp_h_sync_strt_wid = INREG( regs, RADEON_FP_H_SYNC_STRT_WID );
128 	values->fp_v_sync_strt_wid = INREG( regs, RADEON_FP_V_SYNC_STRT_WID );
129 	values->fp2_h_sync_strt_wid = INREG( regs, RADEON_FP_H2_SYNC_STRT_WID );
130 	values->fp2_v_sync_strt_wid = INREG( regs, RADEON_FP_V2_SYNC_STRT_WID );
131 	values->bios_4_scratch =  INREG( regs, RADEON_BIOS_4_SCRATCH );
132 	values->bios_5_scratch =  INREG( regs, RADEON_BIOS_5_SCRATCH );
133 	values->bios_6_scratch =  INREG( regs, RADEON_BIOS_6_SCRATCH );
254 	vuint8 *regs = ai->regs;
258 	OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, RADEON_FP_SEL_CRTC2 );
262 		OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
264 		OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,
266 		OUTREG( regs, RADEON_FP_H2_SYNC_STRT_WID, values->fp2_h_sync_strt_wid );
267 		OUTREG( regs, RADEON_FP_V2_SYNC_STRT_WID, values->fp2_v_sync_strt_wid );
270 		OUTREG( regs, RADEON_FP_H_SYNC_STRT_WID, values->fp_h_sync_strt_wid );
271 		OUTREG( regs, RADEON_FP_V_SYNC_STRT_WID, values->fp_v_sync_strt_wid );
277 		OUTREG( regs, RADEON_GRPH_BUFFER_CNTL,
278 			INREG( regs, RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
282 		OUTREG( regs, RADEON_BIOS_4_SCRATCH, values->bios_4_scratch);
283 		OUTREG( regs, RADEON_BIOS_5_SCRATCH, values->bios_5_scratch);
284 		OUTREG( regs, RADEON_BIOS_6_SCRATCH, values->bios_6_scratch);
289 		//OUTREGP( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl,
295 		old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);
301 				Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );
306 		tmp = INREG( regs, RADEON_LVDS_GEN_CNTL);
311 			OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );
315 				OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );
319 				OUTREG( regs, RADEON_LVDS_GEN_CNTL,	values->lvds_gen_cntl | RADEON_LVDS_BLON );
321 				OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );
327 				Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );