accelerants/radeon/dpms.c

59 	vuint8 *regs = ai->regs;
68 		OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON );
70 		OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON );
78 		old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);
82 			Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );
84 		OUTREGP( regs, RADEON_LVDS_GEN_CNTL, 0,	~(RADEON_LVDS_BLON | RADEON_LVDS_ON) );
87 			Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );
97 	vuint8 *regs = ai->regs;
104 		OUTREGP( regs, RADEON_FP_GEN_CNTL, RADEON_FP_FPON | RADEON_FP_TMDS_EN,
110 		OUTREGP( regs, RADEON_FP_GEN_CNTL, 0, ~RADEON_FP_FPON | RADEON_FP_TMDS_EN );
119 	vuint8 *regs = ai->regs;
126 		OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
127 		OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_FPON, ~RADEON_FP2_FPON);
129 			OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN);
135 		OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN );
136 		OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_FPON);
138 			OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN);
150 	vuint8 *regs = ai->regs;
154 		OUTREGP( regs, RADEON_CRTC_EXT_CNTL, 0, ~RADEON_CRTC_DISPLAY_DIS );
160 		OUTREGP( regs, RADEON_CRTC_EXT_CNTL,
172 	vuint8 *regs = ai->regs;
176 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0,
180 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS),
184 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS),
188 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS),
198 	vuint8 *regs = ai->regs;
204 		OUTREGP( regs, RADEON_CRTC_EXT_CNTL, 0, mask );
207 		OUTREGP( regs, RADEON_CRTC_EXT_CNTL,
211 		OUTREGP( regs, RADEON_CRTC_EXT_CNTL,
215 		OUTREGP( regs, RADEON_CRTC_EXT_CNTL,
224 		OUTREGP( regs, RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B );
230 		OUTREGP( regs, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B,
240 	vuint8 *regs = ai->regs;
246 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0, mask );
249 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), mask );
252 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), mask);
255 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL,
263 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_DISP_REQ_EN_B );
269 		OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_REQ_EN_B,
281 		OUTREG( ai->regs, RADEON_TV_LINEAR_GAIN_SETTINGS,
345 	tmp = INREG( di->regs, RADEON_CRTC_EXT_CNTL );
365 	tmp = INREG( di->regs, RADEON_CRTC2_GEN_CNTL );