accelerants/radeon/SetDisplayMode.c

110 	shared_info *si = ai->si;
132 	fp_info = &si->flatpanels[crtc->flatpanel_port];
179 	internal_tv_encoder = IS_INTERNAL_TV_OUT( si->tv_chip );
189 			&si->pll, tv_params, vc->tv_standard, internal_tv_encoder,
232 		Radeon_CalcCRTPLLDividers( &si->pll, mode, &dividers );
236 	if( (disp_devices & dd_lvds) != 0 && si->flatpanels[0].fixed_dividers ) {
238 		dividers.feedback = si->flatpanels[0].feedback_div;
239 		dividers.post_code = si->flatpanels[0].post_div;
240 		dividers.ref = si->flatpanels[0].ref_div;
306 	RELEASE_BEN( si->cp.lock );
311 	si->active_overlay.crtc_idx = -1;
321 	shared_info *si = ai->si;
327 		| (si->num_crtc > 1 ? RADEON_CRTC2_VBLANK_MASK : 0);
342 	si->enable_virtual_irq = enable;
351 	shared_info *si = ai->si;
356 	ACQUIRE_BEN( si->engine.lock );
365 		RELEASE_BEN( si->engine.lock );
377 		RELEASE_BEN( si->engine.lock );
414 	Radeon_VerifyMultiMode( vc, si, &mode );
417 	vc->independant_heads = vc->assigned_crtc[0] && si->crtc[0].chosen_displays != dd_none;
419 	if( si->num_crtc > 1 )
420 		vc->independant_heads += vc->assigned_crtc[1] && si->crtc[1].chosen_displays != dd_none;
450 		vc->cursor.data = si->local_mem + vc->cursor.fb_offset;
467 		vc->fbc.frame_buffer = si->local_mem + vc->fb_offset;
468 		vc->fbc.frame_buffer_dma = (void *)((uint8 *)si->framebuffer_pci + vc->fb_offset);
490 			si->crtc[0].active_displays = vc->controlled_displays;
494 			si->crtc[1].active_displays = vc->controlled_displays;
499 		vc->used_crtc[0] = vc->assigned_crtc[0] && si->crtc[0].chosen_displays != dd_none;
500 		vc->used_crtc[1] = vc->assigned_crtc[1] && si->crtc[1].chosen_displays != dd_none;
504 			err1 = Radeon_SetMode( ai, &si->crtc[0], &mode, &tv_params );
506 			err2 = Radeon_SetMode( ai, &si->crtc[1], &mode, &tv_params );
529 	si->dac_cntl2 = INREG( ai->regs, RADEON_DAC_CNTL2 );
537 	si->active_vc = -1;
559 	RELEASE_BEN( si->engine.lock );