accelerants/nvidia/SetDisplayMode.c

54 	si->engine.threeD.mode_changing = true;
56 	si->engine.threeD.newmode = 0xffffffff;
59 	si->engine.threeD.clones = 0x00000000;
63 	if (si->ps.secondary_head) head2_interrupt_enable(false);
66 	if (si->ps.tvout) BT_stop_tvout();
70 	if (si->ps.secondary_head) head2_dpms(false, false, false, true);
71 	if (si->ps.tvout) BT_dpms(false);
74 	startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;
77 	nv_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);
185 		si->interlaced_tv_mode = false;
190 		//we need a secondary si->fbc!
215 		if (si->ps.tvout && (target2.flags & TV_BITS)) BT_setmode(target2);
222 		if (si->ps.secondary_head)
279 		if (si->ps.tvout && (target.flags & TV_BITS)) BT_setmode(target);
285 	si->dm = target;
289 	if (si->ps.secondary_head) nv_crtc2_update_fifo();
295 	if (!si->settings.block_acc) {
296 		if (!si->settings.dma_acc)
307 	si->engine.threeD.mem_low = si->fbc.bytes_per_row * si->dm.virtual_height;
308 	if (si->settings.hardcursor) si->engine.threeD.mem_low += 2048;
313 	si->engine.threeD.mem_high = si->ps.memory_size - 1;
316 	if (si->ps.card_arch < NV40A)
317 		si->engine.threeD.mem_high -= PRE_NV40_OFFSET;
319 		si->engine.threeD.mem_high -= NV40_PLUS_OFFSET;
321 	si->engine.threeD.mem_high -= (MAXBUFFERS * 1024 * 1024 * 2); /* see overlay.c file */
324 	SET_DPMS_MODE(si->dpms_flags);
332 	si->engine.threeD.mode_changing = false;
360 	switch(si->dm.space)
380 	switch (si->dm.flags & DUALHEAD_BITS)
384 		if (((si->dm.timing.h_display * 2) + h_display_start) > si->dm.virtual_width)
388 		if ((si->dm.timing.h_display + h_display_start) > si->dm.virtual_width)
392 	if ((si->dm.timing.v_display + v_display_start) > si->dm.virtual_height)
396 	si->dm.h_display_start = h_display_start;
397 	si->dm.v_display_start = v_display_start;
400 	//fixme: seperate both heads: we need a secondary si->fbc!
401 	startadd = v_display_start * si->fbc.bytes_per_row;
403 	startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;
404 	startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3);
408 	if (si->ps.secondary_head) head2_interrupt_enable(false);
410 	switch (si->dm.flags & DUALHEAD_BITS)
439 	if (si->dm.space != B_CMAP8) return;
441 	r=si->color_data;
454 	if (si->dm.flags & DUALHEAD_BITS) head2_palette(r,g,b);
464 	if (si->ps.secondary_head) head2_interrupt_enable(false);
469 	si->dpms_flags = dpms_flags;
499 	if (si->dm.flags & TV_BITS)
504 		if (si->dm.flags & TV_PRIMARY)
508 			if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH)
510 				if (!(si->settings.vga_on_tv))
538 				if (!(si->settings.vga_on_tv))
555 			if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH)
557 				if (!(si->settings.vga_on_tv))
571 				if (!(si->settings.vga_on_tv))
588 	if ((si->ps.secondary_head) && (si->dm.flags & DUALHEAD_BITS))
590 	if (si->dm.flags & TV_BITS)
609 	return si->dpms_flags;