Lines Matching refs:ps
23 si->ps.pins_status = B_ERROR;
63 /* fill out the si->ps struct if possible */
91 /* fill out the si->ps struct */
107 si->ps.pins_status = B_OK;
122 si->ps.f_ref = 0;
124 si->ps.max_system_vco = 0;
125 si->ps.min_system_vco = 0;
126 si->ps.min_pixel_vco = 0;
127 si->ps.min_video_vco = 0;
128 si->ps.std_engine_clock_dh = 0;
129 si->ps.max_dac1_clock_32 = 0;
130 si->ps.max_dac1_clock_32dh = 0;
131 si->ps.memory_size = 0;
132 si->ps.mctlwtst_reg = 0;
133 si->ps.memrdbk_reg = 0;
134 si->ps.option2_reg = 0;
135 si->ps.option3_reg = 0;
136 si->ps.option4_reg = 0;
138 si->ps.v3_option2_reg = 0;
139 si->ps.v3_clk_div = 0;
140 si->ps.v3_mem_type = 0;
142 si->ps.v5_mem_type = 0;
144 si->ps.secondary_head = false;
145 si->ps.tvout = false;
146 si->ps.primary_dvi = false;
147 si->ps.secondary_dvi = false;
148 si->ps.sdram = true;
151 si->ps.max_dac1_clock_32 = pins[22];//ramdac
152 si->ps.max_pixel_vco = (pins[25] << 8) | pins[24];//PCLK
153 si->ps.std_engine_clock = (pins[29] << 8) | pins[28];
154 if ((uint32)((pins[31] << 8) | pins[30]) < si->ps.std_engine_clock)
155 si->ps.std_engine_clock = (pins[31] << 8) | pins[30];
156 if ((uint32)((pins[33] << 8) | pins[32]) < si->ps.std_engine_clock)
157 si->ps.std_engine_clock = (pins[33] << 8) | pins[32];
160 si->ps.max_video_vco = (pins[27] << 8) | pins[26];//LCLK
162 si->ps.option_reg = (pins[53] << 24) | (pins[52] << 16) | (pins[51] << 8) | pins [50];
164 si->ps.max_dac2_clock = (pins[35] << 8) | pins[34];//clkmod
165 si->ps.max_dac2_clock_8 = (pins[37] << 8) | pins[36];//testclk
166 si->ps.max_dac2_clock_16 = (pins[39] << 8) | pins[38];//vgafreq1
167 si->ps.max_dac2_clock_24 = (pins[41] << 8) | pins[40];//vgafreq2
168 si->ps.max_dac2_clock_32 = (pins[55] << 8) | pins[54];//vga clock
169 si->ps.max_dac2_clock_32dh = pins[58];//vid ctrl
171 si->ps.max_dac1_clock = (pins[29] << 8) | pins[28];//clkbase
172 si->ps.max_dac1_clock_8 = (pins[31] << 8) | pins[30];//4mb
173 si->ps.max_dac1_clock_16 = (pins[33] << 8) | pins[32];//8mb
174 si->ps.max_dac1_clock_24 = pins[23];//ramdac type
205 /* fill out the shared info si->ps struct */
206 si->ps.max_pixel_vco = pins[36] + 100;
208 si->ps.max_dac1_clock_8 = pins[37] + 100;
209 si->ps.max_dac1_clock_16 = pins[38] + 100;
210 si->ps.max_dac1_clock_24 = pins[39] + 100;
211 si->ps.max_dac1_clock_32 = pins[40] + 100;
213 si->ps.std_engine_clock = pins[44];
214 if (pins [45] < si->ps.std_engine_clock) si->ps.std_engine_clock = pins[45];
215 if (pins [46] < si->ps.std_engine_clock) si->ps.std_engine_clock = pins[46];
216 if (pins [47] < si->ps.std_engine_clock) si->ps.std_engine_clock = pins[47];
217 if ((si->ps.card_type == G200) && (pins[58] & 0x04))
220 si->ps.std_engine_clock *= 1;
225 si->ps.std_engine_clock *= 3;
227 si->ps.std_engine_clock *= 2;
230 if (pins[52] & 0x20) si->ps.f_ref = 14.31818;
231 else si->ps.f_ref = 27.00000;
234 si->ps.memory_size = 2 << ((pins[55] & 0xc0) >> 6);
236 si->ps.mctlwtst_reg = (pins[51] << 24) | (pins[50] << 16) | (pins[49] << 8) | pins [48];
237 si->ps.memrdbk_reg =
242 si->ps.v3_clk_div = pins[52];
243 si->ps.v3_mem_type = pins[54];
244 si->ps.v3_option2_reg = pins[58];
247 si->ps.tvout = !(pins[59] & 0x01);
251 si->ps.tvout = true;
255 si->ps.secondary_head = false;
256 if (si->ps.card_type >= G400) si->ps.secondary_head = !(pins[59] & 0x01);
259 si->ps.option_reg = 0;
262 if ((si->ps.card_type == G200) && (pins[58] & 0x08))
265 mclk_period = 1000.0 / si->ps.std_engine_clock;
271 mclk_period = 3000.0 / si->ps.std_engine_clock;
273 mclk_period = 2000.0 / si->ps.std_engine_clock;
280 si->ps.option_reg |= (rfhcnt << 15);
284 si->ps.primary_dvi = !(pins[59] & 0x40);
286 si->ps.secondary_dvi = false;
289 si->ps.max_system_vco = si->ps.max_pixel_vco;
290 si->ps.max_dac1_clock = si->ps.max_dac1_clock_8;
291 si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;
292 si->ps.std_engine_clock_dh = si->ps.std_engine_clock;
293 si->ps.sdram = (si->ps.v3_clk_div & 0x10);
295 si->ps.max_dac2_clock_8 = 0;
296 si->ps.max_dac2_clock_24 = 0;
298 si->ps.min_system_vco = 50;
299 si->ps.min_pixel_vco = 50;
301 si->ps.max_video_vco = si->ps.max_pixel_vco;
302 si->ps.min_video_vco = 50;
304 si->ps.max_dac2_clock = 136;
305 si->ps.max_dac2_clock_16 = 136;
306 si->ps.max_dac2_clock_32dh = 136;
307 si->ps.max_dac2_clock_32 = 136;
310 si->ps.option2_reg = 0;
311 si->ps.option3_reg = 0;
312 si->ps.option4_reg = 0;
313 si->ps.v5_mem_type = 0;
330 /* fill out the shared info si->ps struct */
331 if (pins[39] == 0xff) si->ps.max_pixel_vco = 230;
332 else si->ps.max_pixel_vco = 4 * pins[39];
334 if (pins[38] == 0xff) si->ps.max_system_vco = si->ps.max_pixel_vco;
335 else si->ps.max_system_vco = 4 * pins[38];
337 if (pins[40] == 0xff) si->ps.max_dac1_clock_8 = si->ps.max_pixel_vco;
338 else si->ps.max_dac1_clock_8 = 4 * pins[40];
340 if (pins[41] == 0xff) si->ps.max_dac1_clock_16 = si->ps.max_dac1_clock_8;
341 else si->ps.max_dac1_clock_16 = 4 * pins[41];
343 if (pins[42] == 0xff) si->ps.max_dac1_clock_24 = si->ps.max_dac1_clock_16;
344 else si->ps.max_dac1_clock_24 = 4 * pins[42];
346 if (pins[43] == 0xff) si->ps.max_dac1_clock_32 = si->ps.max_dac1_clock_24;
347 else si->ps.max_dac1_clock_32 = 4 * pins[43];
349 if (pins[44] == 0xff) si->ps.max_dac2_clock_16 = si->ps.max_pixel_vco;
350 else si->ps.max_dac2_clock_16 = 4 * pins[44];
352 if (pins[45] == 0xff) si->ps.max_dac2_clock_32 = si->ps.max_dac2_clock_16;
353 else si->ps.max_dac2_clock_32 = 4 * pins[45];
356 si->ps.std_engine_clock = 2 * pins[65];
358 if (pins[92] & 0x01) si->ps.f_ref = 14.31818;
359 else si->ps.f_ref = 27.00000;
361 si->ps.memory_size = 4 << ((pins[92] >> 2) & 0x03);
363 si->ps.mctlwtst_reg = (pins[74] << 24) | (pins[73] << 16) | (pins[72] << 8) | pins [71];
364 si->ps.option3_reg = (pins[70] << 24) | (pins[69] << 16) | (pins[68] << 8) | pins [67];
366 si->ps.memrdbk_reg =
368 si->ps.sdram = (pins[92] & 0x10);
371 si->ps.option_reg = ((pins[53] & 0x38) << 7) | ((pins[53] & 0x40) << 22) | ((pins[53] & 0x80) << 15);
375 switch ((si->ps.option3_reg & 0x0000e000) >> 13)
378 mclk_period = 3000.0 / (si->ps.std_engine_clock * 1);
381 mclk_period = 5000.0 / (si->ps.std_engine_clock * 2);
384 mclk_period = 9000.0 / (si->ps.std_engine_clock * 4);
387 mclk_period = 2000.0 / (si->ps.std_engine_clock * 1);
390 mclk_period = 3000.0 / (si->ps.std_engine_clock * 2);
393 mclk_period = 1000.0 / (si->ps.std_engine_clock * 1);
397 mclk_period = 3000.0 / (si->ps.std_engine_clock * 1);
406 si->ps.option_reg |= (rfhcnt << 15);
409 si->ps.tvout = !(pins[91] & 0x01);
413 si->ps.tvout = true;
417 si->ps.secondary_head = false;
418 if (si->ps.card_type >= G400) si->ps.secondary_head = !(pins[91] & 0x01);
421 si->ps.primary_dvi = !(pins[91] & 0x40);
423 si->ps.secondary_dvi = false;
426 si->ps.max_dac1_clock = si->ps.max_dac1_clock_8;
427 si->ps.max_dac2_clock = si->ps.max_dac2_clock_16;
428 si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;
429 si->ps.max_dac2_clock_32dh = si->ps.max_dac2_clock_32;
430 si->ps.std_engine_clock_dh = si->ps.std_engine_clock;
432 si->ps.max_dac2_clock_8 = 0;
433 si->ps.max_dac2_clock_24 = 0;
435 si->ps.min_system_vco = 50;
436 si->ps.min_pixel_vco = 50;
438 si->ps.max_video_vco = si->ps.max_pixel_vco;
439 si->ps.min_video_vco = 50;
442 si->ps.option2_reg = 0;
443 si->ps.option4_reg = 0;
444 si->ps.v3_option2_reg = 0;
445 si->ps.v3_clk_div = 0;
446 si->ps.v3_mem_type = 0;
447 si->ps.v5_mem_type = 0;
451 if (si->ps.max_dac1_clock > 300)
453 si->ps.card_type = G400MAX;
470 /* fill out the shared info si->ps struct */
474 si->ps.max_system_vco = m_factor * pins[36];
475 si->ps.max_video_vco = m_factor * pins[37];
476 si->ps.max_pixel_vco = m_factor * pins[38];
477 si->ps.min_system_vco = m_factor * pins[121];
478 si->ps.min_video_vco = m_factor * pins[122];
479 si->ps.min_pixel_vco = m_factor * pins[123];
481 if (pins[39] == 0xff) si->ps.max_dac1_clock_8 = si->ps.max_pixel_vco;
482 else si->ps.max_dac1_clock_8 = 4 * pins[39];
484 if (pins[40] == 0xff) si->ps.max_dac1_clock_16 = si->ps.max_dac1_clock_8;
485 else si->ps.max_dac1_clock_16 = 4 * pins[40];
487 if (pins[41] == 0xff) si->ps.max_dac1_clock_24 = si->ps.max_dac1_clock_16;
488 else si->ps.max_dac1_clock_24 = 4 * pins[41];
490 if (pins[42] == 0xff) si->ps.max_dac1_clock_32 = si->ps.max_dac1_clock_24;
491 else si->ps.max_dac1_clock_32 = 4 * pins[42];
493 if (pins[124] == 0xff) si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;
494 else si->ps.max_dac1_clock_32dh = 4 * pins[124];
496 if (pins[43] == 0xff) si->ps.max_dac2_clock_16 = si->ps.max_video_vco;
497 else si->ps.max_dac2_clock_16 = 4 * pins[43];
499 if (pins[44] == 0xff) si->ps.max_dac2_clock_32 = si->ps.max_dac2_clock_16;
500 else si->ps.max_dac2_clock_32 = 4 * pins[44];
502 if (pins[125] == 0xff) si->ps.max_dac2_clock_32dh = si->ps.max_dac2_clock_32;
503 else si->ps.max_dac2_clock_32dh = 4 * pins[125];
505 if (pins[118] == 0xff) si->ps.max_dac1_clock = si->ps.max_dac1_clock_8;
506 else si->ps.max_dac1_clock = 4 * pins[118];
508 if (pins[119] == 0xff) si->ps.max_dac2_clock = si->ps.max_dac1_clock;
509 else si->ps.max_dac2_clock = 4 * pins[119];
511 si->ps.std_engine_clock = 4 * pins[74];
512 si->ps.std_engine_clock_dh = 4 * pins[92];
514 si->ps.memory_size = ((pins[114] & 0x03) + 1) * 8;
518 si->ps.memory_size = 8;
521 if (pins[110] & 0x01) si->ps.f_ref = 14.31818;
522 else si->ps.f_ref = 27.00000;
525 if ((pins[114] & 0x18) == 0x08) si->ps.sdram = false;
526 else si->ps.sdram = true;
528 si->ps.v5_mem_type = (pins[115] << 8) | pins [114];
531 si->ps.option_reg = (pins[51] << 24) | (pins[50] << 16) | (pins[49] << 8) | pins [48];
532 si->ps.option2_reg = (pins[55] << 24) | (pins[54] << 16) | (pins[53] << 8) | pins [52];
533 si->ps.option3_reg = (pins[79] << 24) | (pins[78] << 16) | (pins[77] << 8) | pins [76];
534 si->ps.option4_reg = (pins[87] << 24) | (pins[86] << 16) | (pins[85] << 8) | pins [84];
535 si->ps.mctlwtst_reg = (pins[83] << 24) | (pins[82] << 16) | (pins[81] << 8) | pins [80];
536 si->ps.memrdbk_reg = (pins[91] << 24) | (pins[90] << 16) | (pins[89] << 8) | pins [88];
539 si->ps.secondary_head = (pins[117] & 0x70);
540 si->ps.tvout = (pins[117] & 0x40);
542 si->ps.primary_dvi = (pins[117] & 0x02);
543 si->ps.secondary_dvi = (pins[117] & 0x20);
546 si->ps.max_dac2_clock_8 = 0;
547 si->ps.max_dac2_clock_24 = 0;
550 si->ps.v3_option2_reg = 0;
551 si->ps.v3_clk_div = 0;
552 si->ps.v3_mem_type = 0;
561 switch (si->ps.card_type)
590 si->ps.tvout = false;
591 si->ps.secondary_head = false;
593 if (si->ps.card_type >= G100)
597 si->ps.tvout = true;
599 if (si->ps.card_type >= G400) si->ps.secondary_head = true;
604 si->ps.std_engine_clock = 0;
605 si->ps.std_engine_clock_dh = 0;
606 si->ps.mctlwtst_reg = 0;
607 si->ps.memrdbk_reg = 0;
608 si->ps.option_reg = 0;
609 si->ps.option2_reg = 0;
610 si->ps.option3_reg = 0;
611 si->ps.option4_reg = 0;
612 si->ps.v3_option2_reg = 0;
613 si->ps.v3_clk_div = 0;
614 si->ps.v3_mem_type = 0;
615 si->ps.v5_mem_type = 0;
622 si->ps.f_ref = 14.31818;
624 si->ps.max_system_vco = 220;
625 si->ps.min_system_vco = 110;
626 si->ps.max_pixel_vco = 220;
627 si->ps.min_pixel_vco = 110;
629 si->ps.max_video_vco = 0;
630 si->ps.min_video_vco = 0;
632 si->ps.max_dac1_clock = 220;
633 si->ps.max_dac1_clock_8 = 220;
634 si->ps.max_dac1_clock_16 = 200;
636 si->ps.max_dac1_clock_24 = 180;
637 si->ps.max_dac1_clock_32 = 136;
638 si->ps.max_dac1_clock_32dh = 0;
640 si->ps.max_dac2_clock = 0;
641 si->ps.max_dac2_clock_8 = 0;
642 si->ps.max_dac2_clock_16 = 0;
643 si->ps.max_dac2_clock_24 = 0;
644 si->ps.max_dac2_clock_32 = 0;
646 si->ps.max_dac2_clock_32dh = 0;
647 si->ps.primary_dvi = false;
648 si->ps.secondary_dvi = false;
651 si->ps.memory_size = 2;
654 si->ps.sdram = true;
661 si->ps.f_ref = 14.31818;
663 si->ps.max_system_vco = 220;
664 si->ps.min_system_vco = 110;
665 si->ps.max_pixel_vco = 220;
666 si->ps.min_pixel_vco = 110;
668 si->ps.max_video_vco = 0;
669 si->ps.min_video_vco = 0;
671 si->ps.max_dac1_clock = 220;
672 si->ps.max_dac1_clock_8 = 220;
673 si->ps.max_dac1_clock_16 = 200;
675 si->ps.max_dac1_clock_24 = 180;
676 si->ps.max_dac1_clock_32 = 136;
677 si->ps.max_dac1_clock_32dh = 0;
679 si->ps.max_dac2_clock = 0;
680 si->ps.max_dac2_clock_8 = 0;
681 si->ps.max_dac2_clock_16 = 0;
682 si->ps.max_dac2_clock_24 = 0;
683 si->ps.max_dac2_clock_32 = 0;
685 si->ps.max_dac2_clock_32dh = 0;
686 si->ps.primary_dvi = false;
687 si->ps.secondary_dvi = false;
690 si->ps.memory_size = 4;
693 si->ps.sdram = true;
701 si->ps.f_ref = 27.000;
703 si->ps.max_system_vco = 230;
704 si->ps.min_system_vco = 50;
705 si->ps.max_pixel_vco = 230;
706 si->ps.min_pixel_vco = 50;
708 si->ps.max_video_vco = 230;
709 si->ps.min_video_vco = 50;
711 si->ps.max_dac1_clock = 230;
712 si->ps.max_dac1_clock_8 = 230;
713 si->ps.max_dac1_clock_16 = 230;
715 si->ps.max_dac1_clock_24 = 180;
716 si->ps.max_dac1_clock_32 = 136;
717 si->ps.max_dac1_clock_32dh = 136;
719 si->ps.max_dac2_clock = 136;
720 si->ps.max_dac2_clock_8 = 0;
721 si->ps.max_dac2_clock_16 = 136;
722 si->ps.max_dac2_clock_24 = 0;
723 si->ps.max_dac2_clock_32 = 136;
725 si->ps.max_dac2_clock_32dh = 136;
728 si->ps.primary_dvi = false;
729 si->ps.secondary_dvi = false;
731 si->ps.memory_size = 2;
734 si->ps.sdram = true;
742 si->ps.f_ref = 27.000;
744 si->ps.max_system_vco = 250;
745 si->ps.min_system_vco = 50;
746 si->ps.max_pixel_vco = 250;
747 si->ps.min_pixel_vco = 50;
749 si->ps.max_video_vco = 250;
750 si->ps.min_video_vco = 50;
752 si->ps.max_dac1_clock = 250;
753 si->ps.max_dac1_clock_8 = 250;
754 si->ps.max_dac1_clock_16 = 250;
756 si->ps.max_dac1_clock_24 = 180;
757 si->ps.max_dac1_clock_32 = 136;
758 si->ps.max_dac1_clock_32dh = 136;
760 si->ps.max_dac2_clock = 136;
761 si->ps.max_dac2_clock_8 = 0;
762 si->ps.max_dac2_clock_16 = 136;
763 si->ps.max_dac2_clock_24 = 0;
764 si->ps.max_dac2_clock_32 = 136;
766 si->ps.max_dac2_clock_32dh = 136;
769 si->ps.primary_dvi = false;
770 si->ps.secondary_dvi = false;
772 si->ps.memory_size = 2;
774 si->ps.sdram = !(CFGR(OPTION) & 0x00004000);
782 si->ps.f_ref = 27.000;
784 si->ps.max_system_vco = 300;
785 si->ps.min_system_vco = 50;
786 si->ps.max_pixel_vco = 300;
787 si->ps.min_pixel_vco = 50;
789 si->ps.max_video_vco = 300;
790 si->ps.min_video_vco = 50;
792 si->ps.max_dac1_clock = 300;
793 si->ps.max_dac1_clock_8 = 300;
794 si->ps.max_dac1_clock_16 = 300;
796 si->ps.max_dac1_clock_24 = 230;
797 si->ps.max_dac1_clock_32 = 180;
798 si->ps.max_dac1_clock_32dh = 136;
800 si->ps.max_dac2_clock = 136;
801 si->ps.max_dac2_clock_8 = 0;
802 si->ps.max_dac2_clock_16 = 136;
803 si->ps.max_dac2_clock_24 = 0;
804 si->ps.max_dac2_clock_32 = 136;
806 si->ps.max_dac2_clock_32dh = 136;
809 si->ps.primary_dvi = false;
810 si->ps.secondary_dvi = false;
812 si->ps.memory_size = 4;
814 si->ps.sdram = !(CFGR(OPTION) & 0x00004000);
823 si->ps.f_ref = 27.000;
825 si->ps.max_system_vco = 360;
826 si->ps.min_system_vco = 50;
827 si->ps.max_pixel_vco = 360;
828 si->ps.min_pixel_vco = 50;
830 si->ps.max_video_vco = 360;
831 si->ps.min_video_vco = 50;
833 si->ps.max_dac1_clock = 360;
834 si->ps.max_dac1_clock_8 = 360;
835 si->ps.max_dac1_clock_16 = 360;
837 si->ps.max_dac1_clock_24 = 280;
838 si->ps.max_dac1_clock_32 = 230;
839 si->ps.max_dac1_clock_32dh = 136;
841 si->ps.max_dac2_clock = 136;
842 si->ps.max_dac2_clock_8 = 0;
843 si->ps.max_dac2_clock_16 = 136;
844 si->ps.max_dac2_clock_24 = 0;
845 si->ps.max_dac2_clock_32 = 136;
847 si->ps.max_dac2_clock_32dh = 136;
850 si->ps.primary_dvi = false;
851 si->ps.secondary_dvi = false;
853 si->ps.memory_size = 4;
855 si->ps.sdram = !(CFGR(OPTION) & 0x00004000);
863 si->ps.f_ref = 27.000;
866 si->ps.max_system_vco = 640;
867 si->ps.min_system_vco = 320;
868 si->ps.max_pixel_vco = 640;
869 si->ps.min_pixel_vco = 320;
870 si->ps.max_video_vco = 640;
871 si->ps.min_video_vco = 320;
872 si->ps.max_dac1_clock = 360;
873 si->ps.max_dac1_clock_8 = 360;
874 si->ps.max_dac1_clock_16 = 360;
876 si->ps.max_dac1_clock_24 = 280;
877 si->ps.max_dac1_clock_32 = 230;
878 si->ps.max_dac1_clock_32dh = 180;
880 si->ps.max_dac2_clock = 232;
881 si->ps.max_dac2_clock_8 = 0;
882 si->ps.max_dac2_clock_16 = 232;
883 si->ps.max_dac2_clock_24 = 0;
884 si->ps.max_dac2_clock_32 = 232;
886 si->ps.max_dac2_clock_32dh = 180;
888 si->ps.primary_dvi = false;
889 si->ps.secondary_dvi = false;
891 si->ps.memory_size = 8;
894 // si->ps.sdram = !(CFGR(OPTION) & 0x00004000);
896 si->ps.sdram = true;
904 si->ps.f_ref = 27.000;
907 si->ps.max_system_vco = 768;
908 si->ps.min_system_vco = 384;
909 si->ps.max_pixel_vco = 960;
910 si->ps.min_pixel_vco = 320;
911 si->ps.max_video_vco = 960;
912 si->ps.min_video_vco = 320;
913 si->ps.max_dac1_clock = 360;
914 si->ps.max_dac1_clock_8 = 360;
915 si->ps.max_dac1_clock_16 = 360;
917 si->ps.max_dac1_clock_24 = 280;
918 si->ps.max_dac1_clock_32 = 230;
919 si->ps.max_dac1_clock_32dh = 180;
921 si->ps.max_dac2_clock = 232;
922 si->ps.max_dac2_clock_8 = 0;
923 si->ps.max_dac2_clock_16 = 232;
924 si->ps.max_dac2_clock_24 = 0;
925 si->ps.max_dac2_clock_32 = 232;
927 si->ps.max_dac2_clock_32dh = 180;
929 si->ps.primary_dvi = false;
930 si->ps.secondary_dvi = false;
932 si->ps.memory_size = 8;
935 // si->ps.sdram = !(CFGR(OPTION) & 0x00004000);
937 si->ps.sdram = true;
943 LOG(2,("f_ref: %fMhz\n", si->ps.f_ref));
944 LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco));
945 LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco));
946 LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco));
947 LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco));
948 LOG(2,("max_video_vco: %dMhz\n", si->ps.max_video_vco));
949 LOG(2,("min_video_vco: %dMhz\n", si->ps.min_video_vco));
950 LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock));
951 LOG(2,("std_engine_clock_dh: %dMhz\n", si->ps.std_engine_clock_dh));
952 LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock));
953 LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));
954 LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16));
955 LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24));
956 LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32));
957 LOG(2,("max_dac1_clock_32dh: %dMhz\n", si->ps.max_dac1_clock_32dh));
958 LOG(2,("max_dac2_clock: %dMhz\n", si->ps.max_dac2_clock));
959 LOG(2,("max_dac2_clock_8: %dMhz\n", si->ps.max_dac2_clock_8));
960 LOG(2,("max_dac2_clock_16: %dMhz\n", si->ps.max_dac2_clock_16));
961 LOG(2,("max_dac2_clock_24: %dMhz\n", si->ps.max_dac2_clock_24));
962 LOG(2,("max_dac2_clock_32: %dMhz\n", si->ps.max_dac2_clock_32));
963 LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh));
965 if (si->ps.secondary_head) LOG(2,("present\n")); else LOG(2,("absent\n"));
967 if (si->ps.tvout) LOG(2,("present\n")); else LOG(2,("absent\n"));
969 if ((si->ps.tvout) && (si->ps.card_type < G450))
971 if (si->ps.card_type < G400)
981 if (si->ps.primary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n"));
983 if (si->ps.secondary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n"));
984 LOG(2,("card memory_size: %dMb\n", si->ps.memory_size));
985 LOG(2,("mctlwtst register: $%08x\n", si->ps.mctlwtst_reg));
986 LOG(2,("memrdbk register: $%08x\n", si->ps.memrdbk_reg));
987 LOG(2,("option register: $%08x\n", si->ps.option_reg));
988 LOG(2,("option2 register: $%08x\n", si->ps.option2_reg));
989 LOG(2,("option3 register: $%08x\n", si->ps.option3_reg));
990 LOG(2,("option4 register: $%08x\n", si->ps.option4_reg));
991 LOG(2,("v3_option2_reg: $%02x\n", si->ps.v3_option2_reg));
992 LOG(2,("v3_clock_div: $%02x\n", si->ps.v3_clk_div));
993 LOG(2,("v3_mem_type: $%02x\n", si->ps.v3_mem_type));
994 LOG(2,("v5_mem_type: $%04x\n", si->ps.v5_mem_type));
996 if (si->ps.sdram) LOG(2,("SDRAM card\n")); else LOG(2,("SGRAM card\n"));