accelerants/ati/rage128_mode.cpp

74 CalculateCrtcRegisters(const DisplayModeEx& mode, DisplayParams& params)
101 	params.crtc_gen_cntl = (R128_CRTC_EXT_DISP_EN
105 	params.crtc_h_total_disp = (((mode.timing.h_total / 8) - 1) & 0xffff)
116 	params.crtc_h_sync_strt_wid = (hSyncStart & 0xfff) | (hSyncWidth << 16)
119 	params.crtc_v_total_disp = (((mode.timing.v_total - 1) & 0xffff)
128 	params.crtc_v_sync_strt_wid = ((mode.timing.v_sync_start - 1) & 0xfff)
132 	params.crtc_pitch = mode.timing.h_display / 8;
139 CalculateDDARegisters(const DisplayModeEx& mode, DisplayParams& params)
152 	int vClkFreq = DivideWithRounding(pll.reference_freq * params.feedback_div,
153 		pll.reference_div * params.post_div);
182 	params.dda_config = xClksPerTransferPrecise | (useablePrecision << 16)
184 	params.dda_on_off = (rOn << 16) | rOff;
191 CalculatePLLRegisters(const DisplayModeEx& mode, DisplayParams& params)
229 			params.feedback_div = DivideWithRounding(pll.reference_div * output_freq,
231 			params.post_div = postDividers[j].divider;
242 	params.ppll_ref_div = pll.reference_div;
243 	params.ppll_div_3 = (params.feedback_div | (bitValue << 16));
266 SetRegisters(DisplayParams& params)
297 	OUTREG(R128_DDA_CONFIG, params.dda_config);
298 	OUTREG(R128_DDA_ON_OFF, params.dda_on_off);
303 	OUTREG(R128_CRTC_GEN_CNTL, params.crtc_gen_cntl);
308 	OUTREG(R128_CRTC_H_TOTAL_DISP, params.crtc_h_total_disp);
309 	OUTREG(R128_CRTC_H_SYNC_STRT_WID, params.crtc_h_sync_strt_wid);
310 	OUTREG(R128_CRTC_V_TOTAL_DISP, params.crtc_v_total_disp);
311 	OUTREG(R128_CRTC_V_SYNC_STRT_WID, params.crtc_v_sync_strt_wid);
314 	OUTREG(R128_CRTC_PITCH, params.crtc_pitch);
327 	SetPLLReg(R128_PPLL_REF_DIV, params.ppll_ref_div, R128_PPLL_REF_DIV_MASK);
331 	SetPLLReg(R128_PPLL_DIV_3, params.ppll_div_3,
359 	DisplayParams params;		// where computed parameters are saved
364 		if ( ! CalculateCrtcRegisters(mode, params))
367 		if ( ! CalculatePLLRegisters(mode, params))
370 		if ( ! CalculateDDARegisters(mode, params))
373 		SetRegisters(params);