arch/riscv64/arch_cpu_defs.h

32 		uint64 ie:      4; // interrupt enable
33 		uint64 pie:     4; // previous interrupt enable
34 		uint64 spp:     1; // previous mode (supervisor)
35 		uint64 unused1: 2;
36 		uint64 mpp:     2; // previous mode (machine)
37 		uint64 fs:      2; // FPU status
38 		uint64 xs:      2; // extensions status
39 		uint64 mprv:    1; // modify privilege
40 		uint64 sum:     1; // permit supervisor user memory access
41 		uint64 mxr:     1; // make executable readable
42 		uint64 tvm:     1; // trap virtual memory
43 		uint64 tw:      1; // timeout wait (trap WFI)
44 		uint64 tsr:     1; // trap SRET
45 		uint64 unused2: 9;
46 		uint64 uxl:     2; // U-mode XLEN
47 		uint64 sxl:     2; // S-mode XLEN
48 		uint64 unused3: 27;
49 		uint64 sd:      1; // status dirty
51 	uint64 val;
56 		uint64 ie:      2; // interrupt enable
57 		uint64 unused1: 2;
58 		uint64 pie:     2; // previous interrupt enable
59 		uint64 unused2: 2;
60 		uint64 spp:     1; // previous mode (supervisor)
61 		uint64 unused3: 4;
62 		uint64 fs:      2; // FPU status
63 		uint64 xs:      2; // extensions status
64 		uint64 unused4: 1;
65 		uint64 sum:     1; // permit supervisor user memory access
66 		uint64 mxr:     1; // make executable readable
67 		uint64 unused5: 12;
68 		uint64 uxl:     2; // U-mode XLEN
69 		uint64 unused6: 29;
70 		uint64 sd:      1; // status dirty
72 	uint64 val;
129 		uint64 isValid:    1;
130 		uint64 isRead:     1;
131 		uint64 isWrite:    1;
132 		uint64 isExec:     1;
133 		uint64 isUser:     1;
134 		uint64 isGlobal:   1;
135 		uint64 isAccessed: 1;
136 		uint64 isDirty:    1;
138 		uint64 rsw:        2;
139 		uint64 ppn:       44;
140 		uint64 reserved:  10;
142 	uint64 val;
155 		uint64 ppn:  44;
156 		uint64 asid: 16;
157 		uint64 mode:  4;
159 	uint64 val;
162 static B_ALWAYS_INLINE uint64 VirtAdrPte(uint64 physAdr, uint32 level)
167 static B_ALWAYS_INLINE uint64 VirtAdrOfs(uint64 physAdr)
173 	static B_ALWAYS_INLINE uint64 Name() { \
174 		uint64 x; asm volatile("csrr %0, " #value : "=r" (x)); return x;} \
175 	static B_ALWAYS_INLINE void Set##Name(uint64 x) { \
177 	static B_ALWAYS_INLINE void SetBits##Name(uint64 x) { \
179 	static B_ALWAYS_INLINE void ClearBits##Name(uint64 x) { \
181 	static B_ALWAYS_INLINE uint64 GetAndSetBits##Name(uint64 x) { \
182 		uint64 res; \
186 	static B_ALWAYS_INLINE uint64 GetAndClearBits##Name(uint64 x) { \
187 		uint64 res; \
251 static B_ALWAYS_INLINE void FlushTlbPage(uint64 x) {
253 static B_ALWAYS_INLINE void FlushTlbAllAsid(uint64 asid) {
255 static B_ALWAYS_INLINE void FlushTlbPageAsid(uint64 page, uint64 asid) {
262 static B_ALWAYS_INLINE uint64 Sp() {
263 	uint64 x; asm volatile("mv %0, sp" : "=r" (x)); return x;}
264 static B_ALWAYS_INLINE void SetSp(uint64 x) {
266 static B_ALWAYS_INLINE uint64 Fp() {
267 	uint64 x; asm volatile("mv %0, fp" : "=r" (x)); return x;}
268 static B_ALWAYS_INLINE void SetFp(uint64 x) {
270 static B_ALWAYS_INLINE uint64 Tp() {
271 	uint64 x; asm volatile("mv %0, tp" : "=r" (x)); return x;}
272 static B_ALWAYS_INLINE void SetTp(uint64 x) {
274 static B_ALWAYS_INLINE uint64 Ra() {
275 	uint64 x; asm volatile("mv %0, ra" : "=r" (x)); return x;}
276 static B_ALWAYS_INLINE void SetRa(uint64 x) {