Lines Matching refs:L4_BASE
40 #define L4_BASE 0x48000000
52 #define CM_CLKSEL_PER (L4_BASE + 0x5040)
55 #define CM_FCLKEN_IVA2 (L4_BASE + 0x4000)
56 #define CM_CLKEN_PLL_IVA2 (L4_BASE + 0x4004)
57 #define CM_IDLEST_PLL_IVA2 (L4_BASE + 0x4024)
58 #define CM_CLKSEL1_PLL_IVA2 (L4_BASE + 0x4040)
59 #define CM_CLKSEL2_PLL_IVA2 (L4_BASE + 0x4044)
60 #define CM_CLKEN_PLL_MPU (L4_BASE + 0x4904)
61 #define CM_IDLEST_PLL_MPU (L4_BASE + 0x4924)
62 #define CM_CLKSEL1_PLL_MPU (L4_BASE + 0x4940)
63 #define CM_CLKSEL2_PLL_MPU (L4_BASE + 0x4944)
64 #define CM_FCLKEN1_CORE (L4_BASE + 0x4a00)
65 #define CM_ICLKEN1_CORE (L4_BASE + 0x4a10)
66 #define CM_ICLKEN2_CORE (L4_BASE + 0x4a14)
67 #define CM_CLKSEL_CORE (L4_BASE + 0x4a40)
68 #define CM_FCLKEN_GFX (L4_BASE + 0x4b00)
69 #define CM_ICLKEN_GFX (L4_BASE + 0x4b10)
70 #define CM_CLKSEL_GFX (L4_BASE + 0x4b40)
71 #define CM_FCLKEN_WKUP (L4_BASE + 0x4c00)
72 #define CM_ICLKEN_WKUP (L4_BASE + 0x4c10)
73 #define CM_CLKSEL_WKUP (L4_BASE + 0x4c40)
74 #define CM_IDLEST_WKUP (L4_BASE + 0x4c20)
75 #define CM_CLKEN_PLL (L4_BASE + 0x4d00)
76 #define CM_IDLEST_CKGEN (L4_BASE + 0x4d20)
77 #define CM_CLKSEL1_PLL (L4_BASE + 0x4d40)
78 #define CM_CLKSEL2_PLL (L4_BASE + 0x4d44)
79 #define CM_CLKSEL3_PLL (L4_BASE + 0x4d48)
80 #define CM_FCLKEN_DSS (L4_BASE + 0x4e00)
81 #define CM_ICLKEN_DSS (L4_BASE + 0x4e10)
82 #define CM_CLKSEL_DSS (L4_BASE + 0x4e40)
83 #define CM_FCLKEN_CAM (L4_BASE + 0x4f00)
84 #define CM_ICLKEN_CAM (L4_BASE + 0x4f10)
85 #define CM_CLKSEL_CAM (L4_BASE + 0x4F40)
86 #define CM_FCLKEN_PER (L4_BASE + 0x5000)
87 #define CM_ICLKEN_PER (L4_BASE + 0x5010)
88 #define CM_CLKSEL_PER (L4_BASE + 0x5040)
89 #define CM_CLKSEL1_EMU (L4_BASE + 0x5140)
91 #define PRM_CLKSEL (L4_BASE + 0x306d40)
92 #define PRM_RSTCTRL (L4_BASE + 0x307250)
93 #define PRM_CLKSRC_CTRL (L4_BASE + 0x307270)
96 #define OMAP34XX_GPT1 (L4_BASE + 0x318000)
97 #define OMAP34XX_GPT2 (L4_BASE + 0x1032000)
98 #define OMAP34XX_GPT3 (L4_BASE + 0x1034000)
99 #define OMAP34XX_GPT4 (L4_BASE + 0x1036000)
100 #define OMAP34XX_GPT5 (L4_BASE + 0x1038000)
101 #define OMAP34XX_GPT6 (L4_BASE + 0x103A000)
102 #define OMAP34XX_GPT7 (L4_BASE + 0x103C000)
103 #define OMAP34XX_GPT8 (L4_BASE + 0x103E000)
104 #define OMAP34XX_GPT9 (L4_BASE + 0x1040000)
105 #define OMAP34XX_GPT10 (L4_BASE + 0x86000)
106 #define OMAP34XX_GPT11 (L4_BASE + 0x88000)
107 #define OMAP34XX_GPT12 (L4_BASE + 0x304000)
157 #define TIMER32K_BASE (L4_BASE + 0x320000)
162 #define OMAP_UART1_BASE (L4_BASE + 0x6a000)
163 #define OMAP_UART2_BASE (L4_BASE + 0x6c000)
164 #define OMAP_UART3_BASE (L4_BASE + 0x01020000)
201 #define INTC_BASE (L4_BASE + 0x200000)
228 #define USB_HS_BASE (L4_BASE + 0xab000)
231 #define OTG_BASE (L4_BASE + 0xab400)
241 #define I2C1_BASE (L4_BASE + 0x70000)
242 #define I2C2_BASE (L4_BASE + 0x72000)
243 #define I2C3_BASE (L4_BASE + 0x60000)