graphics/radeon/radeon_interface.h

63 	uint32	loginfo;
64 	uint32	logflow;
65 	uint32	logerror;
275 	uint32 	mem_handle;	// memory handle
276 	uint32	fb_offset;	// offset in frame buffer
311 	uint32		rel_x, rel_y;	// relative position in multi-monitor mode
319 	uint32 max_pll_freq;		// maximum PLL output frequency
320 	uint32 min_pll_freq;		// minimum PLL output frequency
321 	uint32 xclk;				// core frequency
322 	uint32 ref_div;				// default reference divider
323 	uint32 ref_freq;			// PLL reference frequency
339 	uint32 ref_freq;			// reference frequency
340 	uint32 vco_min, vco_max;	// VCO frequency range
341 	uint32 min_ref_div, max_ref_div; // reference divider range
342 	uint32 pll_in_min, pll_in_max; // PLL input frequency range
343 	uint32 extra_feedback_div;	// hardwired divider before feedback divider
344 	uint32 min_feedback_div, max_feedback_div; // feedback divider range
345 	uint32 best_vco;			// preferred VCO frequency (0 for don't care)
350 	uint32 freq;
351 	uint32 value;
357 	uint32 mem_handle;
358 	uint32 mem_offset;
377 	uint32			rel_offset;	// offset of overlay source due to clipping
385 	uint32		id;				// identifier used to know which card the 2D accelerator
397 	uint32		datatype;		// Radeon code for pixel format
399 	uint32		pitch;			// byte offset between two lines
401 	uint32		eff_width, eff_height;	// size of visible area (including both monitors)
402 	uint32		fb_mem_handle;	// memory handle
403 	uint32		fb_offset;		// offset of frame buffer in graphics mem
433 	uint32	auto_flip_reg;		// content of auto_flip_reg
451 		uint32	mem_offset;			// offset in non-local memory
452 		uint32	vm_base;			// base of ring buffer as seen by graphics card
453 		uint32	tail, tail_mask;	// next write position in dwords; mask for wrap-arounds
454 		uint32	size;				// size in dwords
455 		//uint32	head_offset;	// offset for automatically updates head in DMA buffer
457 		//uint32			start_offset;
459 		//uint32	*start;			// pointer to ring buffer
462 		uint32	space;			// known space in ring buffer
463 		uint32 	mem_handle;		// handle of memory of indirect buffers
469 		uint32			scratch_mem_offset;	// offset of scratch registers in feedback memory
470 		uint32			head_mem_offset;	// offset of head register in feedback memory
471 		uint32			scratch_vm_start;	// virtual address of scratch as seen by GC
472 		uint32			head_vm_address;	// virtual address of head as seen by GC
474 		uint32 			mem_handle;		// handle of feedback memory
488 		uint32		mem_offset;		// offset of indirect buffers in non-local memory
489 		uint32		vm_start;		// start of indirect buffers as seen by graphics card
492 		uint32 		mem_handle;		// handle of memory of indirect buffers
501 	uint32		size;				// usable size in bytes
502 	uint32		virtual_addr_start;	// virtual address (for graphics card!)
503 	uint32		virtual_size;		// reserved virtual address space in bytes
559 	uint32	active_vc;			// currently selected virtual card in terms of 2D acceleration
561 	uint32	dac_cntl2;			// content of dac_cntl2 register
562 	uint32	tmds_pll_cntl;			// undocumented here be dragons
563 	uint32	tmds_transmitter_cntl;		// undocumented here be dragons
584 	uint32	magic;				// magic number
591 	uint32	magic;				// magic number
597 	uint32			magic;
599 	uint32			size;		// size in bytes
600 	uint32			offset;		// offset in memory
601 	uint32			handle;		// handle (needed to free memory)
608 	uint32 			magic;
610 	uint32			handle;		// memory handle
616 	uint32 			magic;
622 	uint32 			magic;
628 	uint32 			magic;
631 	uint32 			data;		// read data
637 	uint32 			magic;
640 	uint32 			data;		// data to write
646 	uint32 			magic;
649 	uint32			count;		// size of buffer
656 	uint32 			magic;
659 	uint32			count;		// size of buffer
666 	uint32 			magic;
667 	uint32 			device_id;	// id of device
673 	uint32 			magic;
680 	uint32 			magic;
683 	uint32			int_status;	// content of RADEON_CAP_INT_STATUS
684 	uint32			counter;	// number of capture interrupts so far
689 	uint32 			magic;
690 	uint32			src;		// offset of source data in frame buffer
699 	uint32			magic;