gdb/gdb/ia64-tdep.c

1086 	  /* adds rN = imm14, rM   (or mov rN, rM  when imm14 is 0) */
1090 	  int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1093 	  if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1151 	  /* adds rN = imm14, rM   (or mov rN, rM  when imm14 is 0) */
1155 	  int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1159 	  if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1165 	  else if (qp == 0 && rN == 12 && rM == 12)
1172 	        && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1194 	                  + (rM == 12 ? 0 : mem_stack_frame_size)
1199 	  else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1202 	      /* mov rN, rM where rM is an input register */
1203 	      reg_contents[rN] = rM;
1207 		   rM == 2)
1271 	  /* st8 [rN] = rM
1273 	     st8 [rN] = rM, imm9 */
1275 	  int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1277 	  int indirect = rM < 256 ? reg_contents[rM] : 0;
1279 	      && (rM == unat_save_reg || rM == pr_save_reg))
1285 	      if (rM == unat_save_reg)
1298 		/* st8 [rN] = rM, imm9 */
1304 	  else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1307 	      instores[rM-32] = 1;
1321 	       st1 [rN] = rM
1322 	       st2 [rN] = rM
1323 	       st4 [rN] = rM
1324 	       st8 [rN] = rM
1329 	  int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1331 	  int indirect = rM < 256 ? reg_contents[rM] : 0;
1332 	  if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1334 	      instores[rM-32] = 1;
1366 	  /* st8.spill [rN] = rM
1368 	     st8.spill [rN] = rM, imm9 */
1370 	  int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1372 	  if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1377 	      cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1379 	        /* st8.spill [rN] = rM, imm9 */