Lines Matching refs:bits
126 } bits;
130 #define D8_PS2 bits.D8
131 #define D12_RF1 bits.D12
132 #define D13_RF2 bits.D13
133 #define D14_ACK bits.D14
134 #define D15_NP bits.D15
135 #define D5_FD bits.D5
136 #define D6_HD bits.D6
137 #define D7_PS1 bits.D7
186 } bits;
212 } bits;
216 #define mr_an_enable Mr0.bits.an_enable
217 #define mr_loopback Mr0.bits.loopback
218 #define mr_main_reset Mr0.bits.reset
219 #define mr_restart_an Mr0.bits.restart_an
229 } bits;
233 #define mr_an_complete Mr1.bits.an_complete
234 #define mr_link_ok Mr1.bits.link_ok
252 } bits;
256 #define mr_adv_full_duplex Mr4.bits.full_duplex
257 #define mr_adv_half_duplex Mr4.bits.half_duplex
258 #define mr_adv_sym_pause Mr4.bits.sym_pause
259 #define mr_adv_asym_pause Mr4.bits.asym_pause
260 #define mr_adv_remote_fault1 Mr4.bits.remote_fault1
261 #define mr_adv_remote_fault2 Mr4.bits.remote_fault2
262 #define mr_adv_next_page Mr4.bits.next_page
280 } bits;
284 #define mr_lp_adv_full_duplex Mr5.bits.lp_full_duplex
285 #define mr_lp_adv_half_duplex Mr5.bits.lp_half_duplex
286 #define mr_lp_adv_sym_pause Mr5.bits.lp_sym_pause
287 #define mr_lp_adv_asym_pause Mr5.bits.lp_asym_pause
288 #define mr_lp_adv_remote_fault1 Mr5.bits.lp_remote_fault1
289 #define mr_lp_adv_remote_fault2 Mr5.bits.lp_remote_fault2
290 #define mr_lp_adv_next_page Mr5.bits.lp_next_page
302 } bits;
318 } bits;
336 } bits;
353 } bits;
368 } bits;
372 #define mr_toggle_tx MrMisc.bits.toggle_tx
373 #define mr_toggle_rx MrMisc.bits.toggle_rx
374 #define mr_np_rx MrMisc.bits.np_rx
375 #define mr_page_rx MrMisc.bits.page_rx
376 #define mr_np_loaded MrMisc.bits.np_loaded