Lines Matching refs:sc
274 static void xl_choose_media(struct xl_softc *sc, int *media);
352 xl_wait(struct xl_softc *sc)
357 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
361 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
362 device_printf(sc->xl_dev, "command never completed!\n");
381 struct xl_softc *sc;
384 sc = device_get_softc(dev);
387 val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
388 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
400 struct xl_softc *sc;
402 sc = device_get_softc(dev);
405 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
406 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
413 struct xl_softc *sc;
415 sc = device_get_softc(dev);
426 struct xl_softc *sc;
428 sc = device_get_softc(dev);
441 struct xl_softc *sc;
445 sc = device_get_softc(dev);
446 mii = device_get_softc(sc->xl_miibus);
448 xl_setcfg(sc);
452 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
455 if (sc->xl_type == XL_TYPE_905B) {
464 if (sc->xl_type == XL_TYPE_905B)
467 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
483 struct xl_softc *sc;
487 sc = device_get_softc(dev);
488 mii = device_get_softc(sc->xl_miibus);
491 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
495 if (sc->xl_type == XL_TYPE_905B &&
496 sc->xl_media == XL_MEDIAOPT_10FL) {
498 device_printf(sc->xl_dev, "found 10baseFL\n");
502 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
507 device_printf(sc->xl_dev, "found AUI\n");
512 if (sc->xl_media & XL_MEDIAOPT_BNC) {
514 device_printf(sc->xl_dev, "found BNC\n");
524 xl_eeprom_wait(struct xl_softc *sc)
529 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
536 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
548 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
562 if (xl_eeprom_wait(sc))
565 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
569 if (sc->xl_flags & XL_FLAG_8BITROM)
570 CSR_WRITE_2(sc, XL_W0_EE_CMD,
573 CSR_WRITE_2(sc, XL_W0_EE_CMD,
575 err = xl_eeprom_wait(sc);
578 word = CSR_READ_2(sc, XL_W0_EE_DATA);
590 xl_rxfilter(struct xl_softc *sc)
593 if (sc->xl_type == XL_TYPE_905B)
594 xl_rxfilter_90xB(sc);
596 xl_rxfilter_90x(sc);
604 xl_rxfilter_90x(struct xl_softc *sc)
610 XL_LOCK_ASSERT(sc);
612 ifp = sc->xl_ifp;
615 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
642 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
650 xl_rxfilter_90xB(struct xl_softc *sc)
658 XL_LOCK_ASSERT(sc);
660 ifp = sc->xl_ifp;
663 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
683 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
705 CSR_WRITE_2(sc, XL_COMMAND,
714 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
719 xl_setcfg(struct xl_softc *sc)
723 /*XL_LOCK_ASSERT(sc);*/
726 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
728 if (sc->xl_media & XL_MEDIAOPT_MII ||
729 sc->xl_media & XL_MEDIAOPT_BT4)
731 if (sc->xl_media & XL_MEDIAOPT_BTX)
734 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
735 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
739 xl_setmode(struct xl_softc *sc, int media)
745 XL_LOCK_ASSERT(sc);
748 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
750 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
752 if (sc->xl_media & XL_MEDIAOPT_BT) {
755 sc->xl_xcvr = XL_XCVR_10BT;
764 if (sc->xl_media & XL_MEDIAOPT_BFX) {
767 sc->xl_xcvr = XL_XCVR_100BFX;
775 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
778 sc->xl_xcvr = XL_XCVR_AUI;
787 sc->xl_xcvr = XL_XCVR_AUI;
796 if (sc->xl_media & XL_MEDIAOPT_BNC) {
799 sc->xl_xcvr = XL_XCVR_COAX;
811 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
815 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
816 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
824 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
826 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
831 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
835 xl_reset(struct xl_softc *sc)
839 XL_LOCK_ASSERT(sc);
842 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
843 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
853 if (sc->xl_flags & XL_FLAG_USE_MMIO)
858 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
863 device_printf(sc->xl_dev, "reset didn't complete\n");
872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
874 xl_wait(sc);
875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
876 xl_wait(sc);
878 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
879 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
881 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
882 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
883 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
885 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
929 xl_mediacheck(struct xl_softc *sc)
938 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
943 if (sc->xl_xcvr <= XL_XCVR_AUTO)
946 device_printf(sc->xl_dev,
947 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
948 device_printf(sc->xl_dev,
952 if (sc->xl_type == XL_TYPE_905B &&
953 sc->xl_media & XL_MEDIAOPT_10FL)
955 device_printf(sc->xl_dev,
957 device_printf(sc->xl_dev,
959 device_printf(sc->xl_dev,
963 xl_choose_xcvr(sc, 1);
967 xl_choose_xcvr(struct xl_softc *sc, int verbose)
976 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
981 sc->xl_media = XL_MEDIAOPT_BT;
982 sc->xl_xcvr = XL_XCVR_10BT;
984 device_printf(sc->xl_dev,
989 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
990 sc->xl_xcvr = XL_XCVR_10BT;
992 device_printf(sc->xl_dev,
996 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
997 sc->xl_xcvr = XL_XCVR_10BT;
999 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1002 sc->xl_media = XL_MEDIAOPT_10FL;
1003 sc->xl_xcvr = XL_XCVR_AUI;
1005 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1019 sc->xl_media = XL_MEDIAOPT_MII;
1020 sc->xl_xcvr = XL_XCVR_MII;
1022 device_printf(sc->xl_dev, "guessing MII\n");
1026 sc->xl_media = XL_MEDIAOPT_BT4;
1027 sc->xl_xcvr = XL_XCVR_MII;
1029 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1037 sc->xl_media = XL_MEDIAOPT_BTX;
1038 sc->xl_xcvr = XL_XCVR_AUTO;
1040 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1043 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1044 sc->xl_xcvr = XL_XCVR_AUTO;
1046 device_printf(sc->xl_dev,
1050 device_printf(sc->xl_dev,
1052 sc->xl_media = XL_MEDIAOPT_BT;
1066 struct xl_softc *sc;
1072 sc = device_get_softc(dev);
1073 sc->xl_dev = dev;
1077 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1079 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1083 sc->xl_flags = 0;
1085 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1088 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1093 sc->xl_flags |= XL_FLAG_8BITROM;
1095 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1101 sc->xl_flags |= XL_FLAG_FUNCREG;
1107 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1110 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1112 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1114 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1116 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1119 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1123 sc->xl_flags |= XL_FLAG_PHYOK;
1133 sc->xl_flags |= XL_FLAG_NO_MMIO;
1144 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1148 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1151 if (sc->xl_res != NULL) {
1152 sc->xl_flags |= XL_FLAG_USE_MMIO;
1158 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1159 if (sc->xl_res == NULL) {
1168 sc->xl_btag = rman_get_bustag(sc->xl_res);
1169 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1171 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1173 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1176 if (sc->xl_fres == NULL) {
1182 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1183 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1188 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1190 if (sc->xl_irq == NULL) {
1197 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1203 ifp->if_softc = sc;
1207 XL_LOCK(sc);
1208 xl_reset(sc);
1209 XL_UNLOCK(sc);
1214 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1220 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1221 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1233 &sc->xl_ldata.xl_rx_tag);
1239 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1240 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1241 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1244 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1245 sc->xl_ldata.xl_rx_tag = NULL;
1249 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1250 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1252 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1255 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1256 sc->xl_ldata.xl_rx_dmamap);
1257 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1258 sc->xl_ldata.xl_rx_tag = NULL;
1265 &sc->xl_ldata.xl_tx_tag);
1271 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1272 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1273 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1276 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1277 sc->xl_ldata.xl_tx_tag = NULL;
1281 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1282 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1284 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1287 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1288 sc->xl_ldata.xl_tx_dmamap);
1289 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1290 sc->xl_ldata.xl_tx_tag = NULL;
1300 NULL, &sc->xl_mtag);
1307 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1321 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1322 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1323 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1324 sc->xl_type = XL_TYPE_905B;
1326 sc->xl_type = XL_TYPE_90X;
1329 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1331 sc->xl_pmcap = pmcap;
1332 sc->xl_flags |= XL_FLAG_WOL;
1334 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1341 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1346 if (sc->xl_type == XL_TYPE_905B) {
1354 if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1372 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1374 device_printf(dev, "media options word: %x\n", sc->xl_media);
1376 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1377 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1378 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1379 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1383 sc->xl_xcvr = XL_XCVR_10BT;
1386 xl_mediacheck(sc);
1388 if (sc->xl_media & XL_MEDIAOPT_MII ||
1389 sc->xl_media & XL_MEDIAOPT_BTX ||
1390 sc->xl_media & XL_MEDIAOPT_BT4) {
1393 xl_setcfg(sc);
1401 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1403 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1405 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1418 if (sc->xl_xcvr == XL_XCVR_AUTO)
1419 xl_choose_xcvr(sc, bootverbose);
1424 if (sc->xl_media & XL_MEDIAOPT_BT) {
1427 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1428 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1429 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1430 ifmedia_add(&sc->ifmedia,
1434 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1438 if (sc->xl_type == XL_TYPE_905B &&
1439 sc->xl_media == XL_MEDIAOPT_10FL) {
1442 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1443 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1445 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1446 ifmedia_add(&sc->ifmedia,
1451 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1455 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1458 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1461 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1464 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1468 xl_choose_media(sc, &media);
1470 if (sc->xl_miibus == NULL)
1471 ifmedia_set(&sc->ifmedia, media);
1474 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1476 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1484 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1485 NULL, xl_intr, sc, &sc->xl_intrhand);
1506 xl_choose_media(struct xl_softc *sc, int *media)
1509 XL_LOCK(sc);
1511 switch (sc->xl_xcvr) {
1514 xl_setmode(sc, *media);
1517 if (sc->xl_type == XL_TYPE_905B &&
1518 sc->xl_media == XL_MEDIAOPT_10FL) {
1520 xl_setmode(sc, *media);
1523 xl_setmode(sc, *media);
1528 xl_setmode(sc, *media);
1539 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1540 sc->xl_xcvr);
1549 XL_UNLOCK(sc);
1562 struct xl_softc *sc;
1566 sc = device_get_softc(dev);
1567 ifp = sc->xl_ifp;
1569 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1576 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1586 XL_LOCK(sc);
1587 xl_stop(sc);
1588 XL_UNLOCK(sc);
1589 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1590 callout_drain(&sc->xl_tick_callout);
1593 if (sc->xl_miibus)
1594 device_delete_child(dev, sc->xl_miibus);
1596 ifmedia_removeall(&sc->ifmedia);
1598 if (sc->xl_intrhand)
1599 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1600 if (sc->xl_irq)
1601 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1602 if (sc->xl_fres != NULL)
1604 XL_PCI_FUNCMEM, sc->xl_fres);
1605 if (sc->xl_res)
1606 bus_release_resource(dev, res, rid, sc->xl_res);
1611 if (sc->xl_mtag) {
1612 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1613 bus_dma_tag_destroy(sc->xl_mtag);
1615 if (sc->xl_ldata.xl_rx_tag) {
1616 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1617 sc->xl_ldata.xl_rx_dmamap);
1618 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1619 sc->xl_ldata.xl_rx_dmamap);
1620 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1622 if (sc->xl_ldata.xl_tx_tag) {
1623 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1624 sc->xl_ldata.xl_tx_dmamap);
1625 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1626 sc->xl_ldata.xl_tx_dmamap);
1627 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1630 mtx_destroy(&sc->xl_mtx);
1639 xl_list_tx_init(struct xl_softc *sc)
1645 XL_LOCK_ASSERT(sc);
1647 cd = &sc->xl_cdata;
1648 ld = &sc->xl_ldata;
1651 error = bus_dmamap_create(sc->xl_mtag, 0,
1674 xl_list_tx_init_90xB(struct xl_softc *sc)
1680 XL_LOCK_ASSERT(sc);
1682 cd = &sc->xl_cdata;
1683 ld = &sc->xl_ldata;
1686 error = bus_dmamap_create(sc->xl_mtag, 0,
1721 xl_list_rx_init(struct xl_softc *sc)
1728 XL_LOCK_ASSERT(sc);
1730 cd = &sc->xl_cdata;
1731 ld = &sc->xl_ldata;
1735 error = bus_dmamap_create(sc->xl_mtag, 0,
1739 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1764 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1771 XL_LOCK_ASSERT(sc);
1782 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1786 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1793 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1795 c->xl_map = sc->xl_tmpmap;
1796 sc->xl_tmpmap = map;
1801 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1806 xl_rx_resync(struct xl_softc *sc)
1811 XL_LOCK_ASSERT(sc);
1813 pos = sc->xl_cdata.xl_rx_head;
1824 sc->xl_cdata.xl_rx_head = pos;
1834 xl_rxeof(struct xl_softc *sc)
1837 struct ifnet *ifp = sc->xl_ifp;
1843 XL_LOCK_ASSERT(sc);
1845 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1847 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1850 if (sc->rxcycles <= 0)
1852 sc->rxcycles--;
1855 cur_rx = sc->xl_cdata.xl_rx_head;
1856 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1878 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1879 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1889 device_printf(sc->xl_dev,
1893 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1894 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1899 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1910 if (xl_newbuf(sc, cur_rx)) {
1913 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1914 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1917 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1918 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1940 XL_UNLOCK(sc);
1942 XL_LOCK(sc);
1965 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1966 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1968 xl_wait(sc);
1969 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1970 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1983 struct xl_softc *sc = (struct xl_softc *)arg;
1985 XL_LOCK(sc);
1986 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
1987 xl_rxeof(sc);
1988 XL_UNLOCK(sc);
1996 xl_txeof(struct xl_softc *sc)
1999 struct ifnet *ifp = sc->xl_ifp;
2001 XL_LOCK_ASSERT(sc);
2012 while (sc->xl_cdata.xl_tx_head != NULL) {
2013 cur_tx = sc->xl_cdata.xl_tx_head;
2015 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2018 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2019 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2021 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2027 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2028 sc->xl_cdata.xl_tx_free = cur_tx;
2031 if (sc->xl_cdata.xl_tx_head == NULL) {
2032 sc->xl_wdog_timer = 0;
2033 sc->xl_cdata.xl_tx_tail = NULL;
2035 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2036 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2037 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2038 sc->xl_cdata.xl_tx_head->xl_phys);
2039 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2045 xl_txeof_90xB(struct xl_softc *sc)
2048 struct ifnet *ifp = sc->xl_ifp;
2051 XL_LOCK_ASSERT(sc);
2053 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2055 idx = sc->xl_cdata.xl_tx_cons;
2056 while (idx != sc->xl_cdata.xl_tx_prod) {
2057 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2064 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2066 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2073 sc->xl_cdata.xl_tx_cnt--;
2077 if (sc->xl_cdata.xl_tx_cnt == 0)
2078 sc->xl_wdog_timer = 0;
2079 sc->xl_cdata.xl_tx_cons = idx;
2091 xl_txeoc(struct xl_softc *sc)
2095 XL_LOCK_ASSERT(sc);
2097 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2101 device_printf(sc->xl_dev,
2103 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2104 xl_wait(sc);
2105 if (sc->xl_type == XL_TYPE_905B) {
2106 if (sc->xl_cdata.xl_tx_cnt) {
2110 i = sc->xl_cdata.xl_tx_cons;
2111 c = &sc->xl_cdata.xl_tx_chain[i];
2112 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2114 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2115 sc->xl_wdog_timer = 5;
2118 if (sc->xl_cdata.xl_tx_head != NULL) {
2119 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2120 sc->xl_cdata.xl_tx_head->xl_phys);
2121 sc->xl_wdog_timer = 5;
2128 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2130 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2131 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2132 device_printf(sc->xl_dev,
2133 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2135 CSR_WRITE_2(sc, XL_COMMAND,
2136 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2137 if (sc->xl_type == XL_TYPE_905B) {
2138 CSR_WRITE_2(sc, XL_COMMAND,
2141 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2142 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2144 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2145 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2151 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2158 struct xl_softc *sc = arg;
2159 struct ifnet *ifp = sc->xl_ifp;
2162 XL_LOCK(sc);
2166 XL_UNLOCK(sc);
2174 status = CSR_READ_2(sc, XL_STATUS);
2177 CSR_WRITE_2(sc, XL_COMMAND,
2180 status = atomic_get((int32 *)&sc->xl_intr_status);
2187 if (xl_rxeof(sc) == 0) {
2188 while (xl_rx_resync(sc))
2189 xl_rxeof(sc);
2194 if (sc->xl_type == XL_TYPE_905B)
2195 xl_txeof_90xB(sc);
2197 xl_txeof(sc);
2202 xl_txeoc(sc);
2207 xl_init_locked(sc);
2212 xl_stats_update(sc);
2214 status = CSR_READ_2(sc, XL_STATUS);
2217 CSR_WRITE_2(sc, XL_COMMAND,
2224 if (sc->xl_type == XL_TYPE_905B)
2230 XL_UNLOCK(sc);
2237 struct xl_softc *sc = ifp->if_softc;
2240 XL_LOCK(sc);
2243 XL_UNLOCK(sc);
2250 struct xl_softc *sc = ifp->if_softc;
2253 XL_LOCK_ASSERT(sc);
2255 sc->rxcycles = count;
2256 rx_npkts = xl_rxeof(sc);
2257 if (sc->xl_type == XL_TYPE_905B)
2258 xl_txeof_90xB(sc);
2260 xl_txeof(sc);
2263 if (sc->xl_type == XL_TYPE_905B)
2272 status = CSR_READ_2(sc, XL_STATUS);
2274 CSR_WRITE_2(sc, XL_COMMAND,
2279 xl_txeoc(sc);
2284 xl_init_locked(sc);
2288 xl_stats_update(sc);
2298 struct xl_softc *sc = xsc;
2301 XL_LOCK_ASSERT(sc);
2303 if (sc->xl_miibus != NULL) {
2304 mii = device_get_softc(sc->xl_miibus);
2308 xl_stats_update(sc);
2309 if (xl_watchdog(sc) == EJUSTRETURN)
2312 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2316 xl_stats_update(struct xl_softc *sc)
2318 struct ifnet *ifp = sc->xl_ifp;
2323 XL_LOCK_ASSERT(sc);
2333 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2347 CSR_READ_1(sc, XL_W4_BADSSD);
2356 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2359 struct ifnet *ifp = sc->xl_ifp;
2363 XL_LOCK_ASSERT(sc);
2365 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2366 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2390 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2391 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2407 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2411 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2414 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2416 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2417 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2421 if (sc->xl_type == XL_TYPE_905B) {
2453 struct xl_softc *sc = ifp->if_softc;
2455 XL_LOCK(sc);
2457 if (sc->xl_type == XL_TYPE_905B)
2462 XL_UNLOCK(sc);
2468 struct xl_softc *sc = ifp->if_softc;
2474 XL_LOCK_ASSERT(sc);
2483 if (sc->xl_cdata.xl_tx_free == NULL) {
2484 xl_txeoc(sc);
2485 xl_txeof(sc);
2486 if (sc->xl_cdata.xl_tx_free == NULL) {
2492 start_tx = sc->xl_cdata.xl_tx_free;
2495 sc->xl_cdata.xl_tx_free != NULL;) {
2502 cur_tx = sc->xl_cdata.xl_tx_free;
2505 error = xl_encap(sc, cur_tx, &m_head);
2515 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2551 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2552 xl_wait(sc);
2554 if (sc->xl_cdata.xl_tx_head != NULL) {
2555 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2556 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2558 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2560 sc->xl_cdata.xl_tx_tail = cur_tx;
2562 sc->xl_cdata.xl_tx_head = start_tx;
2563 sc->xl_cdata.xl_tx_tail = cur_tx;
2565 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2567 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2568 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2570 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2577 sc->xl_wdog_timer = 5;
2594 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2600 struct xl_softc *sc = ifp->if_softc;
2606 XL_LOCK_ASSERT(sc);
2612 idx = sc->xl_cdata.xl_tx_prod;
2613 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2616 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2617 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2627 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2630 error = xl_encap(sc, cur_tx, &m_head);
2652 sc->xl_cdata.xl_tx_cnt++;
2671 sc->xl_cdata.xl_tx_prod = idx;
2673 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2679 sc->xl_wdog_timer = 5;
2685 struct xl_softc *sc = xsc;
2687 XL_LOCK(sc);
2688 xl_init_locked(sc);
2689 XL_UNLOCK(sc);
2693 xl_init_locked(struct xl_softc *sc)
2695 struct ifnet *ifp = sc->xl_ifp;
2699 XL_LOCK_ASSERT(sc);
2706 xl_stop(sc);
2709 xl_reset(sc);
2711 if (sc->xl_miibus == NULL) {
2712 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2713 xl_wait(sc);
2715 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2716 xl_wait(sc);
2719 if (sc->xl_miibus != NULL)
2720 mii = device_get_softc(sc->xl_miibus);
2726 if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2728 CSR_READ_2(sc, XL_W7_BM_PME);
2729 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2734 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2735 IF_LLADDR(sc->xl_ifp)[i]);
2740 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2743 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2744 xl_wait(sc);
2745 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2746 xl_wait(sc);
2749 error = xl_list_rx_init(sc);
2751 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2753 xl_stop(sc);
2758 if (sc->xl_type == XL_TYPE_905B)
2759 error = xl_list_tx_init_90xB(sc);
2761 error = xl_list_tx_init(sc);
2763 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2765 xl_stop(sc);
2775 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2778 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2789 if (sc->xl_type == XL_TYPE_905B) {
2790 CSR_WRITE_2(sc, XL_COMMAND,
2795 xl_rxfilter(sc);
2807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2808 xl_wait(sc);
2809 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2811 xl_wait(sc);
2813 if (sc->xl_type == XL_TYPE_905B) {
2815 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2817 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2818 xl_wait(sc);
2819 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2820 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2821 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2822 xl_wait(sc);
2830 if (sc->xl_xcvr == XL_XCVR_COAX)
2831 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2833 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2842 if (sc->xl_type == XL_TYPE_905B)
2843 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2846 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2848 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2853 xl_stats_update(sc);
2855 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2866 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2870 if (sc->xl_flags & XL_FLAG_FUNCREG)
2871 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2875 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2879 xl_wait(sc);
2880 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2881 xl_wait(sc);
2893 sc->xl_wdog_timer = 0;
2894 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2903 struct xl_softc *sc = ifp->if_softc;
2907 XL_LOCK(sc);
2909 if (sc->xl_miibus != NULL)
2910 mii = device_get_softc(sc->xl_miibus);
2912 ifm = &sc->ifmedia;
2921 xl_setmode(sc, ifm->ifm_media);
2922 XL_UNLOCK(sc);
2926 if (sc->xl_media & XL_MEDIAOPT_MII ||
2927 sc->xl_media & XL_MEDIAOPT_BTX ||
2928 sc->xl_media & XL_MEDIAOPT_BT4) {
2930 xl_init_locked(sc);
2932 xl_setmode(sc, ifm->ifm_media);
2935 XL_UNLOCK(sc);
2946 struct xl_softc *sc = ifp->if_softc;
2951 XL_LOCK(sc);
2953 if (sc->xl_miibus != NULL)
2954 mii = device_get_softc(sc->xl_miibus);
2957 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2960 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2972 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2978 if (sc->xl_type == XL_TYPE_905B &&
2979 sc->xl_media == XL_MEDIAOPT_10FL) {
2981 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3012 XL_UNLOCK(sc);
3018 struct xl_softc *sc = ifp->if_softc;
3025 XL_LOCK(sc);
3028 (ifp->if_flags ^ sc->xl_if_flags) &
3030 xl_rxfilter(sc);
3032 xl_init_locked(sc);
3035 xl_stop(sc);
3037 sc->xl_if_flags = ifp->if_flags;
3038 XL_UNLOCK(sc);
3043 XL_LOCK(sc);
3045 xl_rxfilter(sc);
3046 XL_UNLOCK(sc);
3050 if (sc->xl_miibus != NULL)
3051 mii = device_get_softc(sc->xl_miibus);
3054 &sc->ifmedia, command);
3069 XL_LOCK(sc);
3071 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3073 XL_UNLOCK(sc);
3077 XL_LOCK(sc);
3078 CSR_WRITE_2(sc, XL_COMMAND,
3080 CSR_WRITE_2(sc, XL_COMMAND,
3082 if (sc->xl_flags & XL_FLAG_FUNCREG)
3083 bus_space_write_4(sc->xl_ftag,
3084 sc->xl_fhandle, 4, 0x8000);
3085 XL_UNLOCK(sc);
3089 XL_LOCK(sc);
3104 XL_UNLOCK(sc);
3115 xl_watchdog(struct xl_softc *sc)
3117 struct ifnet *ifp = sc->xl_ifp;
3121 XL_LOCK_ASSERT(sc);
3123 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3126 xl_rxeof(sc);
3127 xl_txeoc(sc);
3129 if (sc->xl_type == XL_TYPE_905B) {
3130 xl_txeof_90xB(sc);
3131 if (sc->xl_cdata.xl_tx_cnt == 0)
3134 xl_txeof(sc);
3135 if (sc->xl_cdata.xl_tx_head == NULL)
3139 device_printf(sc->xl_dev,
3146 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3147 device_printf(sc->xl_dev, "watchdog timeout\n");
3150 device_printf(sc->xl_dev,
3154 xl_init_locked(sc);
3157 if (sc->xl_type == XL_TYPE_905B)
3171 xl_stop(struct xl_softc *sc)
3174 struct ifnet *ifp = sc->xl_ifp;
3176 XL_LOCK_ASSERT(sc);
3178 sc->xl_wdog_timer = 0;
3180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3181 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3182 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3183 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3184 xl_wait(sc);
3185 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3186 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3191 xl_wait(sc);
3192 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3193 xl_wait(sc);
3196 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3197 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3198 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3199 if (sc->xl_flags & XL_FLAG_FUNCREG)
3200 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3203 callout_stop(&sc->xl_tick_callout);
3209 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3210 bus_dmamap_unload(sc->xl_mtag,
3211 sc->xl_cdata.xl_rx_chain[i].xl_map);
3212 bus_dmamap_destroy(sc->xl_mtag,
3213 sc->xl_cdata.xl_rx_chain[i].xl_map);
3214 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3215 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3218 if (sc->xl_ldata.xl_rx_list != NULL)
3219 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3224 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3225 bus_dmamap_unload(sc->xl_mtag,
3226 sc->xl_cdata.xl_tx_chain[i].xl_map);
3227 bus_dmamap_destroy(sc->xl_mtag,
3228 sc->xl_cdata.xl_tx_chain[i].xl_map);
3229 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3230 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3233 if (sc->xl_ldata.xl_tx_list != NULL)
3234 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3253 struct xl_softc *sc;
3255 sc = device_get_softc(dev);
3257 XL_LOCK(sc);
3258 xl_stop(sc);
3259 xl_setwol(sc);
3260 XL_UNLOCK(sc);
3268 struct xl_softc *sc;
3271 sc = device_get_softc(dev);
3272 ifp = sc->xl_ifp;
3274 XL_LOCK(sc);
3278 xl_init_locked(sc);
3281 XL_UNLOCK(sc);
3287 xl_setwol(struct xl_softc *sc)
3292 if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3295 ifp = sc->xl_ifp;
3298 CSR_READ_2(sc, XL_W7_BM_PME);
3302 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3305 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3307 pmstat = pci_read_config(sc->xl_dev,
3308 sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3313 pci_write_config(sc->xl_dev,
3314 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);