graphics/radeon/vip.c

23 static bool Radeon_VIPWaitForIdle( device_info *di );
24 static status_t RADEON_VIPFifoIdle(device_info *di, uint8 channel);
30 	device_info *di, uint channel, uint address, uint32 *data )
32 	vuint8 *regs = di->regs;
34 	Radeon_WaitForFifo( di, 2 );
38 	if( !Radeon_VIPWaitForIdle( di ))
42 	Radeon_WaitForFifo( di, 2 );
45 	//Radeon_WaitForIdle( di, false, false );
50 	if( !Radeon_VIPWaitForIdle( di ))
53 	//Radeon_WaitForIdle( di, false, false );
56 	Radeon_WaitForFifo( di, 2 );
59 	//Radeon_WaitForIdle( di, false, false );
66 	if( !Radeon_VIPWaitForIdle( di ))
71 	Radeon_WaitForFifo( di, 2 );
80 	device_info *di, uint channel, uint address, uint32 *data, bool lock )
85 		ACQUIRE_BEN( di->si->cp.lock );
87 	res = do_VIPRead( di, channel, address, data );
90 		RELEASE_BEN( di->si->cp.lock );
97 static bool do_VIPFifoRead(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer)
99    	vuint8 *regs = di->regs;
110 	Radeon_WaitForFifo( di, 2);
114 	while(B_BUSY == (status = RADEON_VIPFifoIdle( di , 0xff)));
123 	Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
132 	Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
135 	while(B_BUSY == (status = RADEON_VIPFifoIdle( di , 0xff)));
140 	Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
146 	Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
159 	while(B_BUSY == (status = RADEON_VIPFifoIdle( di , 0xff)));
170 bool Radeon_VIPFifoRead(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock)
175 		ACQUIRE_BEN( di->si->cp.lock );
177 	res = do_VIPFifoRead( di, channel, address, count, buffer );
180 		RELEASE_BEN( di->si->cp.lock );
189 static bool do_VIPWrite( device_info *di, uint8 channel, uint address, uint32 data )
191 	vuint8 *regs = di->regs;
193 	Radeon_WaitForFifo( di, 2 );
196 	if( !Radeon_VIPWaitForIdle( di )) return false;
200 	Radeon_WaitForFifo( di, 2 );
203 	return Radeon_VIPWaitForIdle( di );
208 bool Radeon_VIPWrite(device_info *di, uint8 channel, uint address, uint32 data, bool lock )
215 		ACQUIRE_BEN( di->si->cp.lock );
217 	res = do_VIPWrite( di, channel, address, data );
220 		RELEASE_BEN( di->si->cp.lock );
226 static bool do_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer)
228 	vuint8 *regs = di->regs;
235     Radeon_WaitForFifo( di, 2 );
238     while(B_BUSY == (status = RADEON_VIPFifoIdle( di, 0x0f)));
249 		Radeon_WaitForFifo( di, 2);
252 		while(B_BUSY == (status = RADEON_VIPFifoIdle( di, 0x0f)));
263 bool Radeon_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock)
270 		ACQUIRE_BEN( di->si->cp.lock );
272 	Radeon_VIPReset( di, false);
273 	res = do_VIPFifoWrite( di, channel, address, count, buffer );
276 		RELEASE_BEN( di->si->cp.lock );
284 	device_info *di, bool lock )
286 	vuint8 *regs = di->regs;
289 		ACQUIRE_BEN( di->si->cp.lock );
291 	Radeon_WaitForFifo( di, 5 ); // Radeon_WaitForIdle( di, false, false );
292 	switch(di->asic){
329 		RELEASE_BEN( di->si->cp.lock );
336 	device_info *di )
338 	vuint8 *regs = di->regs;
341 	//Radeon_WaitForIdle( di, false, false );
354 static status_t RADEON_VIPFifoIdle(device_info *di, uint8 channel)
356 	vuint8 *regs = di->regs;
372 	device_info *di )
380 		res = Radeon_VIPIdle( di );
399 	device_info *di, uint32 device_id )
406 	if( !di->has_vip ) {
411 	ACQUIRE_BEN( di->si->cp.lock );
413 	Radeon_VIPReset( di, false );
419 		if( !Radeon_VIPRead( di, channel, RADEON_VIP_VENDOR_DEVICE_ID, &cur_device_id, false ))	{
427 			RELEASE_BEN( di->si->cp.lock );
432 	RELEASE_BEN( di->si->cp.lock );