graphics/radeon/CP_setup.c

83 		mem_type = di->si->nonlocal_type; \
84 	res = mem_alloc( di->memmgr[mem_type], asize, NULL, handle, offset );
89 	((uint8 *)(memory_type == mt_local ? di->si->local_mem : \
90 	(memory_type == mt_PCI ? di->pci_gart.buffer.ptr : di->agp_gart.buffer.ptr)) \
96 	(di->si->memory[(memory_type)].virtual_addr_start + (offset))
102 		di->memmgr[ mem_type == mt_nonlocal ? di->si->nonlocal_type : mem_type], \
108 void Radeon_DiscardAllIndirectBuffers( device_info *di );
113 void Radeon_FlushPixelCache( device_info *di );
119 void Radeon_WaitForIdle( device_info *di, bool acquire_lock, bool keep_lock )
122 		ACQUIRE_BEN( di->si->cp.lock );
124 	Radeon_WaitForFifo( di, 64 );
130 			if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) {
131 				Radeon_FlushPixelCache( di );
134 					RELEASE_BEN( di->si->cp.lock );
143 			INREG( di->regs, RADEON_RBBM_STATUS ),
144 			INREG( di->regs, RADEON_CP_STAT ),
145 			INREG( di->regs, RADEON_AIC_TLB_ADDR ),
146 			INREG( di->regs, RADEON_AIC_TLB_DATA ));
148 		LOG( di->si->log, _Radeon_WaitForIdle );
150 		Radeon_ResetEngine( di );
157 void Radeon_WaitForFifo( device_info *di, int entries )
163 			int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
171 		LOG( di->si->log, _Radeon_WaitForFifo );
173 		Radeon_ResetEngine( di );
178 void Radeon_FlushPixelCache( device_info *di )
182 	OUTREGP( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL,
188 		if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT )
195 	LOG( di->si->log, _Radeon_FlushPixelCache );
202 void Radeon_ResetEngine( device_info *di )
204 	vuint8 *regs = di->regs;
205 	shared_info *si = di->si;
211 	Radeon_FlushPixelCache( di );
214 	RADEONPllErrataAfterIndex( regs, di->asic );	// drm has no errata here!
215 	mclk_cntl = Radeon_INPLL( regs, di->asic, RADEON_MCLK_CNTL );
218 	Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl |
253 	Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl );
255    	//RADEONPllErrataAfterIndex( regs, di->asic ); // drm doesn't do this here!
258 	if ( di->acc_dma )
274 		Radeon_DiscardAllIndirectBuffers( di );
283 static void loadMicroEngineRAMData( device_info *di )
290 	switch( di->asic ) {
306 	Radeon_WaitForIdle( di, false, false );
308 	OUTREG( di->regs, RADEON_CP_ME_RAM_ADDR, 0 );
311 		OUTREG( di->regs, RADEON_CP_ME_RAM_DATAH, microcode[i][1] );
312 		OUTREG( di->regs, RADEON_CP_ME_RAM_DATAL, microcode[i][0] );
317 static status_t initRingBuffer( device_info *di, int aring_size )
320 	shared_info *si = di->si;
322 	vuint8 *regs = di->regs;
371 static void uninitRingBuffer( device_info *di )
373 	vuint8 *regs = di->regs;
376 	Radeon_ResetEngine( di );
383 	FREE_MEM( mt_nonlocal, di->si->cp.ring.mem_handle );
386 static status_t initCPFeedback( device_info *di )
388 	CP_info *cp = &di->si->cp;
389 	vuint8 *regs = di->regs;
427 static void uninitCPFeedback( device_info *di )
429 	vuint8 *regs = di->regs;
434 	FREE_MEM( mt_PCI, di->si->cp.feedback.mem_handle );
437 static status_t initIndirectBuffers( device_info *di )
439 	CP_info *cp = &di->si->cp;
477 static void uninitIndirectBuffers( device_info *di )
479 	FREE_MEM( mt_nonlocal, di->si->cp.buffers.mem_handle );
483 status_t Radeon_InitCP( device_info *di )
493 	memset( &di->si->cp, 0, sizeof( di->si->cp ));
495 	if( (res = INIT_BEN( di->si->cp.lock, "Radeon CP" )) < 0 )
505     set_sem_owner( di->si->cp.lock.sem, thinfo.team );
508 	if ( di->acc_dma ) loadMicroEngineRAMData( di );
511 	Radeon_ResetEngine( di );
516 	OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
517 	INREG( di->regs, RADEON_CP_CSQ_CNTL );
520 	Radeon_ResetEngine( di );
522 	if ( di->acc_dma )
524 		res = initRingBuffer( di, CP_RING_SIZE );
528 		res = initCPFeedback( di );
532 		res = initIndirectBuffers( di );
537 		Radeon_WaitForIdle( di, false, false );
540 		OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM );
543 		OUTREGP( di->regs, RADEON_BUS_CNTL, 0, ~RADEON_BUS_MASTER_DIS );
550 	OUTREG( di->regs, RADEON_ISYNC_CNTL,
556 	SHOW_FLOW( 3, "bus_cntl=%lx", INREG( di->regs, RADEON_BUS_CNTL ));
565 	uninitCPFeedback( di );
567 	uninitRingBuffer( di );
569 	DELETE_BEN( di->si->cp.lock );
575 void Radeon_UninitCP( device_info *di )
577 	vuint8 *regs = di->regs;
580 	Radeon_ResetEngine( di );
587 	if ( di->acc_dma )
589 		uninitRingBuffer( di );
590 		uninitCPFeedback( di );
591 		uninitIndirectBuffers( di );
594 	DELETE_BEN( di->si->cp.lock );
601 void Radeon_DiscardAllIndirectBuffers( device_info *di )
603 	CP_info *cp = &di->si->cp;
635 void Radeon_SetDynamicClock( device_info *di, int mode)
637     vuint8 *regs = di->regs;
638     radeon_type asic = di->asic;
643 		if ( di->num_crtc != 2 ) {
711 			if ( di->num_crtc != 2 ) {
744 			if (di->is_igp) {
781 		if ( di->num_crtc != 2 ) {
864 					if (di->ram.width == 64) {