Lines Matching defs:function
46 pci_read_config(uint8 virtualBus, uint8 device, uint8 function, uint8 offset,
56 if (gPCI->ReadConfig(domain, bus, device, function, offset, size,
65 pci_write_config(uint8 virtualBus, uint8 device, uint8 function, uint8 offset,
73 gPCI->WriteConfig(domain, bus, device, function, offset, size, value);
78 pci_find_capability(uchar virtualBus, uchar device, uchar function,
86 return gPCI->FindCapability(domain, bus, device, function, capID, offset);
91 pci_reserve_device(uchar virtualBus, uchar device, uchar function,
97 TRACE(("pci_reserve_device(%d, %d, %d, %s)\n", virtualBus, device, function,
110 // domain, bus, device, function, driverName, nodeCookie));
124 {B_PCI_DEVICE_FUNCTION, B_UINT8_TYPE, {ui8: function}},
189 pci_unreserve_device(uchar virtualBus, uchar device, uchar function,
196 function, driverName));
202 // domain, bus, device, function, driverName, nodeCookie));
216 {B_PCI_DEVICE_FUNCTION, B_UINT8_TYPE, {ui8: function}},
287 pci_update_interrupt_line(uchar virtualBus, uchar device, uchar function,
295 return gPCI->UpdateInterruptLine(domain, bus, device, function,
732 for (int function = 0; function < numFunctions; function++) {
733 uint16 device_id = ReadConfig(domain, bus, dev, function,
738 uint8 baseClass = ReadConfig(domain, bus, dev, function,
740 uint8 subClass = ReadConfig(domain, bus, dev, function,
746 uint8 headerType = ReadConfig(domain, bus, dev, function,
752 domain, bus, dev, function));
756 ReadConfig(domain, bus, dev, function, PCI_command, 2),
757 ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
758 ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
759 ReadConfig(domain, bus, dev, function, PCI_subordinate_bus, 1)));
763 pcicmd = ReadConfig(domain, bus, dev, function, PCI_command, 2);
766 WriteConfig(domain, bus, dev, function, PCI_command, 2, pcicmd);
769 WriteConfig(domain, bus, dev, function, PCI_primary_bus, 1, 0);
770 WriteConfig(domain, bus, dev, function, PCI_secondary_bus, 1, 0);
771 WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, 0);
776 ReadConfig(domain, bus, dev, function, PCI_command, 2),
777 ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
778 ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
779 ReadConfig(domain, bus, dev, function, PCI_subordinate_bus, 1)));
792 for (int function = 0; function < numFunctions; function++) {
793 uint16 deviceID = ReadConfig(domain, bus, dev, function,
798 uint8 baseClass = ReadConfig(domain, bus, dev, function,
800 uint8 subClass = ReadConfig(domain, bus, dev, function,
806 uint8 headerType = ReadConfig(domain, bus, dev, function,
812 domain, bus, dev, function));
815 WriteConfig(domain, bus, dev, function, PCI_primary_bus, 1, bus);
816 WriteConfig(domain, bus, dev, function, PCI_secondary_bus, 1,
818 WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, 255);
822 pcicmd = ReadConfig(domain, bus, dev, function, PCI_command, 2);
824 WriteConfig(domain, bus, dev, function, PCI_command, 2, pcicmd);
829 ReadConfig(domain, bus, dev, function, PCI_command, 2),
830 ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
831 ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
832 ReadConfig(domain, bus, dev, function, PCI_subordinate_bus, 1)));
838 WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, lastUsedBusNumber);
843 ReadConfig(domain, bus, dev, function, PCI_command, 2),
844 ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
845 ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
846 ReadConfig(domain, bus, dev, function, PCI_subordinate_bus, 1)));
878 for (int function = 0; function < numFunctions; function++) {
879 uint16 deviceId = ReadConfig(domain, bus, dev, function,
884 pci_fixup_device(this, domain, bus, dev, function);
886 uint8 baseClass = ReadConfig(domain, bus, dev, function,
890 uint8 subClass = ReadConfig(domain, bus, dev, function,
897 uint8 headerType = ReadConfig(domain, bus, dev, function,
902 domain, bus, dev, function, headerType);
907 int busBehindBridge = ReadConfig(domain, bus, dev, function,
928 dev->device, dev->function, PCI_bridge_control, 2);
940 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
943 dev->function, PCI_bridge_control, 2);
946 dev->device, dev->function, bridgeControlOld,
971 dev->function, PCI_status, 2);
972 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
976 "0x%04x\n", dev->domain, dev->bus, dev->device, dev->function,
996 dev->device, dev->function, PCI_secondary_status, 2);
997 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1002 dev->device, dev->function, secondaryStatus);
1019 dev->device, dev->function, PCI_bridge_control, 2);
1020 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1025 dev->function, bridgeControl);
1064 for (int function = 0; function < numFunctions; function++)
1065 _DiscoverDevice(bus, dev, function);
1075 PCI::_DiscoverDevice(PCIBus *bus, uint8 dev, uint8 function)
1077 FLOW("PCI: DiscoverDevice, domain %u, bus %u, dev %u, func %u\n", bus->domain, bus->bus, dev, function);
1079 uint16 deviceID = ReadConfig(bus->domain, bus->bus, dev, function,
1084 PCIDev *newDev = _CreateDevice(bus, dev, function);
1086 uint8 baseClass = ReadConfig(bus->domain, bus->bus, dev, function,
1088 uint8 subClass = ReadConfig(bus->domain, bus->bus, dev, function,
1090 uint8 headerType = ReadConfig(bus->domain, bus->bus, dev, function,
1094 uint8 secondaryBus = ReadConfig(bus->domain, bus->bus, dev, function,
1123 PCI::_CreateDevice(PCIBus *parent, uint8 device, uint8 function)
1125 FLOW("PCI: CreateDevice, domain %u, bus %u, dev %u, func %u:\n", parent->domain, parent->bus, device, function);
1137 newDev->function = function;
1175 uint32 oldValue = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1177 WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1179 uint32 newValue = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1181 WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1196 uint32 oldValue = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1198 WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1200 uint32 newValue = ReadConfig(dev->domain, dev->bus, dev->device, dev->function,
1202 WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
1224 dev->function, PCI_vendor_id, 2);
1226 dev->function, PCI_device_id, 2);
1229 dev->info.function = dev->function;
1231 dev->function, PCI_revision, 1);
1233 dev->function, PCI_class_api, 1);
1235 dev->function, PCI_class_sub, 1);
1237 dev->function, PCI_class_base, 1);
1239 dev->function, PCI_line_size, 1);
1241 dev->function, PCI_latency, 1);
1245 dev->function, PCI_header_type, 1);
1247 dev->function, PCI_bist, 1);
1261 dev->function, PCI_command, 2);
1262 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1277 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1288 dev->device, dev->function, PCI_cardbus_cis, 4);
1290 dev->device, dev->function, PCI_subsystem_id, 2);
1292 dev->bus, dev->device, dev->function, PCI_subsystem_vendor_id, 2);
1294 dev->device, dev->function, PCI_interrupt_line, 1);
1296 dev->device, dev->function, PCI_interrupt_pin, 1);
1298 dev->device, dev->function, PCI_min_grant, 1);
1300 dev->device, dev->function, PCI_max_latency, 1);
1308 dev->function, PCI_command, 2);
1309 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1323 WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
1334 dev->device, dev->function, PCI_primary_bus, 1);
1336 dev->device, dev->function, PCI_secondary_bus, 1);
1338 dev->bus, dev->device, dev->function, PCI_subordinate_bus, 1);
1340 dev->bus, dev->device, dev->function, PCI_secondary_latency, 1);
1342 dev->device, dev->function, PCI_io_base, 1);
1344 dev->device, dev->function, PCI_io_limit, 1);
1346 dev->bus, dev->device, dev->function, PCI_secondary_status, 2);
1348 dev->device, dev->function, PCI_memory_base, 2);
1350 dev->device, dev->function, PCI_memory_limit, 2);
1352 dev->bus, dev->device, dev->function, PCI_prefetchable_memory_base, 2);
1354 dev->domain, dev->bus, dev->device, dev->function,
1357 dev->domain, dev->bus, dev->device, dev->function,
1360 dev->domain, dev->bus, dev->device, dev->function,
1363 dev->bus, dev->device, dev->function, PCI_io_base_upper16, 2);
1365 dev->bus, dev->device, dev->function, PCI_io_limit_upper16, 2);
1367 dev->device, dev->function, PCI_interrupt_line, 1);
1369 dev->device, dev->function, PCI_interrupt_pin, 1);
1371 dev->device, dev->function, PCI_bridge_control, 2);
1373 dev->device, dev->function, PCI_sub_device_id_1, 2);
1375 dev->bus, dev->device, dev->function, PCI_sub_vendor_id_1, 2);
1383 dev->device, dev->function, PCI_sub_device_id_2, 2);
1385 dev->bus, dev->device, dev->function, PCI_sub_vendor_id_2, 2);
1387 dev->device, dev->function, PCI_primary_bus_2, 1);
1389 dev->device, dev->function, PCI_secondary_bus_2, 1);
1391 dev->bus, dev->device, dev->function, PCI_subordinate_bus_2, 1);
1393 dev->bus, dev->device, dev->function, PCI_secondary_latency_2, 1);
1396 dev->device, dev->function, PCI_memory_base0_2, 4);
1398 dev->device, dev->function, PCI_memory_limit0_2, 4);
1400 dev->bus, dev->device, dev->function, PCI_memory_base1_2, 4);
1402 dev->bus, dev->device, dev->function, PCI_memory_limit1_2, 4);
1404 dev->device, dev->function, PCI_io_base0_2, 4);
1406 dev->device, dev->function, PCI_io_limit0_2, 4);
1408 dev->bus, dev->device, dev->function, PCI_io_base1_2, 4);
1410 dev->bus, dev->device, dev->function, PCI_io_limit1_2, 4);
1412 dev->bus, dev->device, dev->function, PCI_secondary_status_2, 2);
1414 dev->bus, dev->device, dev->function, PCI_bridge_control_2, 2);
1454 PCI::ReadConfig(int domain, uint8 bus, uint8 device, uint8 function,
1462 || function > 7
1466 dprintf("PCI: can't read config for domain %d, bus %u, device %u, function %u, offset %u, size %u\n",
1467 domain, bus, device, function, offset, size);
1472 device, function, offset, size, value);
1477 PCI::ReadConfig(int domain, uint8 bus, uint8 device, uint8 function,
1481 if (ReadConfig(domain, bus, device, function, offset, size, &value)
1494 device->function, offset, size, &value) != B_OK)
1502 PCI::WriteConfig(int domain, uint8 bus, uint8 device, uint8 function,
1510 || function > 7
1514 dprintf("PCI: can't write config for domain %d, bus %u, device %u, function %u, offset %u, size %u\n",
1515 domain, bus, device, function, offset, size);
1520 device, function, offset, size, value);
1528 device->function, offset, size, value);
1533 PCI::FindCapability(int domain, uint8 bus, uint8 device, uint8 function,
1537 TRACE_CAP("PCI: FindCapability() ERROR %u:%u:%u capability %#02x offset NULL pointer\n", bus, device, function, capID);
1541 uint16 status = ReadConfig(domain, bus, device, function, PCI_status, 2);
1543 TRACE_CAP("PCI: find_pci_capability ERROR %u:%u:%u capability %#02x not supported\n", bus, device, function, capID);
1547 uint8 headerType = ReadConfig(domain, bus, device, function,
1554 capPointer = ReadConfig(domain, bus, device, function,
1558 capPointer = ReadConfig(domain, bus, device, function,
1562 TRACE_CAP("PCI: find_pci_capability ERROR %u:%u:%u capability %#02x unknown header type\n", bus, device, function, capID);
1568 TRACE_CAP("PCI: find_pci_capability ERROR %u:%u:%u capability %#02x empty list\n", bus, device, function, capID);
1573 if (ReadConfig(domain, bus, device, function, capPointer, 1) == capID) {
1578 capPointer = ReadConfig(domain, bus, device, function, capPointer + 1,
1586 TRACE_CAP("PCI: find_pci_capability ERROR %u:%u:%u capability %#02x circular list\n", bus, device, function, capID);
1595 device->function, capID, offset);
1600 PCI::FindDevice(int domain, uint8 bus, uint8 device, uint8 function)
1602 return _FindDevice(fRootBus, domain, bus, device, function);
1608 uint8 function)
1616 && child->function == function)
1622 function);
1631 return _FindDevice(current->next, domain, bus, device, function);
1638 PCI::UpdateInterruptLine(int domain, uint8 bus, uint8 _device, uint8 function,
1641 PCIDev *device = FindDevice(domain, bus, _device, function);