bus_managers/firewire/fwohci.cpp

206 #define	OHCI_DMACTL(off)	(off)
207 #define	OHCI_DMACTLCLR(off)	(off + 4)
208 #define	OHCI_DMACMD(off)	(off + 0xc)
209 #define	OHCI_DMAMATCH(off)	(off + 0x10)
879 	uint32_t off;
892 		off = OHCI_ATQOFF;
894 		off = OHCI_ATSOFF;
1043 		OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
1047 					OREAD(sc, OHCI_DMACTL(off)));
1048 		OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1049 		OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1085 	uint32_t off;
1091 		off = OHCI_ATQOFF;
1094 		off = OHCI_ATSOFF;
1121 			OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1125 			OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1382 	uint32_t off = 0;
1393 			off = OHCI_ITOFF(dmach);
1397 	if(off == 0){
1441 	uint32_t off = 0;
1451 		off = OHCI_ARQOFF;
1453 		off = OHCI_ARSOFF;
1457 				off = OHCI_IROFF(dmach);
1462 	if(off == 0){
1542 		OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1544 	OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
2285 	uint32_t off, cntl, stat, cmd, match;
2288 		off = OHCI_ATQOFF;
2290 		off = OHCI_ATSOFF;
2292 		off = OHCI_ARQOFF;
2294 		off = OHCI_ARSOFF;
2296 		off = OHCI_ITCTL(ch - ITX_CH);
2298 		off = OHCI_IRCTL(ch - IRX_CH);
2300 	cntl = stat = OREAD(sc, off);
2301 	cmd = OREAD(sc, off + 0xc);
2302 	match = OREAD(sc, off + 0x10);
2334 	uint32_t cmd, off;
2336 		off = OHCI_ATQOFF;
2339 		off = OHCI_ATSOFF;
2342 		off = OHCI_ARQOFF;
2345 		off = OHCI_ARSOFF;
2348 		off = OHCI_ITCTL(ch - ITX_CH);
2351 		off = OHCI_IRCTL(ch - IRX_CH);
2354 	cmd = OREAD(sc, off + 0xc);
2507 	 * Set root hold-off bit so that non cyclemaster capable node
2722     struct fwohcidb_tr *db_tr, uint32_t off, int wake)
2733 		OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
2745 	uint32_t stat, off, status, event;
2753 		off = OHCI_ARQOFF;
2755 		off = OHCI_ARSOFF;
2771 		if (off == OHCI_ARQOFF)
2921 				    OREAD(sc, OHCI_DMACTL(off)),
2931 				    off, 1);
2940 				fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
2967 					OREAD(sc, OHCI_DMACTL(off)));
2973 		fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
2981 	OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);