Lines Matching defs:db_tr
483 struct fwohcidb_tr *db_tr;
566 for( i = 0, db_tr = sc->atrq.top; (uint)i < sc->atrq.ndb ;
567 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
568 db_tr->xfer = NULL;
570 for( i = 0, db_tr = sc->atrs.top; (uint)i < sc->atrs.ndb ;
571 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
572 db_tr->xfer = NULL;
839 struct fwohcidb_tr *db_tr;
846 db_tr = (struct fwohcidb_tr *)arg;
847 db = &db_tr->db[db_tr->dbcnt];
855 db_tr->dbcnt++;
862 db_tr->dbcnt++;
883 struct fwohcidb_tr *db_tr;
903 db_tr = dbch->top;
915 db_tr->xfer = xfer;
921 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
945 db = &db_tr->db[0];
963 db_tr->dbcnt = 2;
964 db = &db_tr->db[db_tr->dbcnt];
967 fwohci_execute_db(db_tr, &xfer->send);
970 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
972 fwohci_execute_db, db_tr,
976 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
978 fwohci_execute_db2, db_tr,
1001 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
1005 for (i = 2; i < db_tr->dbcnt; i++)
1006 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
1010 if (maxdesc < db_tr->dbcnt) {
1011 maxdesc = db_tr->dbcnt;
1016 LAST_DB(db_tr, db);
1020 STAILQ_NEXT(db_tr, link)->bus_addr);
1023 fsegment = db_tr->dbcnt;
1026 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1029 dbch->pdb_tr = db_tr;
1030 db_tr = STAILQ_NEXT(db_tr, link);
1031 if(db_tr != dbch->bottom){
1053 dbch->top = db_tr;
1222 struct fwohcidb_tr *db_tr;
1228 /* for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1229 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1231 db_tr->buf != NULL) {
1232 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1233 db_tr->buf, dbch->xferq.psize);
1234 db_tr->buf = NULL;
1235 else if (db_tr->dma_map != NULL)
1236 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1245 db_tr = STAILQ_FIRST(&dbch->db_trq);
1247 free(db_tr);
1256 struct fwohcidb_tr *db_tr;
1283 db_tr = (struct fwohcidb_tr *)
1285 if(db_tr == NULL){
1289 memset(db_tr, 0, sizeof(struct fwohcidb_tr) * dbch->ndb);
1295 free(db_tr);
1300 db_tr->dbcnt = 0;
1301 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1302 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1307 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1314 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1318 ].start = (caddr_t)db_tr;
1321 ].end = (caddr_t)db_tr;
1323 db_tr++;
1383 struct fwohcidb_tr *db_tr;
1407 db_tr = dbch->top;
1409 fwohci_add_tx_buf(dbch, db_tr, idb);
1410 if(STAILQ_NEXT(db_tr, link) == NULL){
1413 db = db_tr->db;
1414 ldesc = db_tr->dbcnt - 1;
1416 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1429 db_tr = STAILQ_NEXT(db_tr, link);
1442 struct fwohcidb_tr *db_tr;
1480 db_tr = dbch->top;
1493 //fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1495 db_tr->buf = (caddr_t)buf_virt;
1498 db_tr->dbcnt = 1;
1503 db_tr->dbcnt = 0;
1504 dsiz[db_tr->dbcnt] = sizeof(uint32_t);
1505 dbuf[db_tr->dbcnt++] = sc->dummy_dma.bus_addr;
1506 dsiz[db_tr->dbcnt] = ir->psize;
1508 db_tr->buf = (char*)fwdma_v_addr(ir->buf, idb);
1509 dbuf[db_tr->dbcnt] = fwdma_bus_addr(
1512 db_tr->dbcnt++;
1514 fwohci_set_rx_buf(ir, db_tr, dbuf, dsiz);
1516 if (STAILQ_NEXT(db_tr, link) == NULL)
1518 db = db_tr->db;
1519 ldesc = db_tr->dbcnt - 1;
1521 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1532 db_tr = STAILQ_NEXT(db_tr, link);
1535 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1708 // struct fwohcidb_tr *db_tr;
1747 db_tr = (struct fwohcidb_tr *)(chunk->start);
1748 db_tr->dbcnt = 1;
1749 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1750 chunk->mbuf, fwohci_execute_db2, db_tr,
1752 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
2221 struct fwohcidb_tr *db_tr;
2238 db_tr = (struct fwohcidb_tr *)chunk->end;
2239 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2245 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2247 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2406 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2436 db_tr->bus_addr,
2525 struct fwohcidb_tr *db_tr, *fdb_tr;
2538 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2541 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2544 db = db_tr->db;
2545 fp = (struct fw_pkt *)db_tr->buf;
2566 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2571 bulkxfer->end = (caddr_t)db_tr;
2572 db_tr = STAILQ_NEXT(db_tr, link);
2583 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2585 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2591 fwohci_add_tx_buf(fwohci_softc::fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2594 struct fwohcidb *db = db_tr->db;
2603 db_tr->buf = (char*)fwdma_v_addr(it->buf, poffset);
2604 db_tr->dbcnt = 3;
2623 fwohci_set_rx_buf(struct fw_xferq *ir, struct fwohcidb_tr *db_tr,
2627 struct fwohcidb *db = db_tr->db;
2629 for(i = 0 ; i < db_tr->dbcnt ; i++){
2637 ldesc = db_tr->dbcnt - 1;
2722 struct fwohcidb_tr *db_tr, uint32_t off, int wake)
2724 struct fwohcidb *db = &db_tr->db[0];
2730 dbch->bottom = db_tr;
2739 struct fwohcidb_tr *db_tr;
2761 db_tr = dbch->top;
2766 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2767 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2773 db_tr->bus_addr, status, resCount);
2776 ld = (uint8_t *)db_tr->buf;
2782 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2810 bcopy(db_tr->buf, p, rlen);
2836 dbch->pdb_tr = db_tr;
2860 dbch->pdb_tr = db_tr;
2877 dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2940 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
2943 if (dbch->pdb_tr != db_tr)
2944 printf("pdb_tr != db_tr\n");
2945 db_tr = STAILQ_NEXT(db_tr, link);
2946 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2948 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2951 dbch->top = db_tr;
2973 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
2974 db_tr = STAILQ_NEXT(db_tr, link);
2975 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2979 dbch->top = db_tr;