accelerants/radeon_hd/encoder.cpp

578 		DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
645 				args.v3.ucPanelMode = panelMode;
685 			args.v3.ucAction = command;
686 			args.v3.usPixelClock = B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
689 				args.v3.ucPanelMode = panelMode;
691 				args.v3.ucEncoderMode
695 			if (args.v3.ucEncoderMode == ATOM_ENCODER_MODE_DP
696 				|| args.v3.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST) {
697 				args.v3.ucLaneNum = dpInfo->laneCount;
699 				args.v3.ucLaneNum = 8;
701 				args.v3.ucLaneNum = 4;
703 			if ((args.v3.ucEncoderMode == ATOM_ENCODER_MODE_DP
704 				|| args.v3.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)
709 			args.v3.acConfig.ucDigSel = encoder_pick_dig(connectorIndex);
714 					args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
717 					args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
721 					args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
724 					args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
727 					args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
730 					args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
838 		EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
880 					args.v3.sExtEncoder.ucAction = command;
882 						args.v3.sExtEncoder.usConnectorId
885 						args.v3.sExtEncoder.usPixelClock
889 					args.v3.sExtEncoder.ucEncoderMode
894 							args.v3.sExtEncoder.ucConfig
897 							args.v3.sExtEncoder.ucConfig
903 						args.v3.sExtEncoder.ucLaneNum = 8;
905 						args.v3.sExtEncoder.ucLaneNum = 4;
913 							args.v3.sExtEncoder.ucConfig
918 							args.v3.sExtEncoder.ucConfig
923 							args.v3.sExtEncoder.ucConfig
932 							args.v3.sExtEncoder.ucBitPerColor
936 							args.v3.sExtEncoder.ucBitPerColor
941 							args.v3.sExtEncoder.ucBitPerColor
945 							args.v3.sExtEncoder.ucBitPerColor
949 							args.v3.sExtEncoder.ucBitPerColor
953 							args.v3.sExtEncoder.ucBitPerColor
1210 		DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1376 					args.v3.ucAction = command;
1378 						args.v3.usInitInfo
1382 						args.v3.asMode.ucLaneSel = laneNumber;
1383 						args.v3.asMode.ucLaneSet = laneSet;
1386 							args.v3.usPixelClock
1389 							args.v3.usPixelClock = B_HOST_TO_LENDIAN_INT16(
1392 							args.v3.usPixelClock
1398 						args.v3.ucLaneNum = dpLaneCount;
1400 						args.v3.ucLaneNum = 8;
1402 						args.v3.ucLaneNum = 4;
1405 						args.v3.acConfig.ucLinkSel = 1;
1407 						args.v3.acConfig.ucEncoderSel = 1;
1415 						args.v3.acConfig.ucRefClkSource = 2; // EXT clock
1417 						args.v3.acConfig.ucRefClkSource = pll->id;
1421 							args.v3.acConfig.ucTransmitterSel = 0;
1424 							args.v3.acConfig.ucTransmitterSel = 1;
1427 							args.v3.acConfig.ucTransmitterSel = 2;
1432 						args.v3.acConfig.fCoherentMode = 1;
1437 							args.v3.acConfig.fCoherentMode = 1;
1440 							args.v3.acConfig.fDualLinkConnector = 1;