Lines Matching refs:UCHAR
51 #ifndef UCHAR
52 typedef unsigned char UCHAR;
202 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */
203 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */
213 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
228 UCHAR ucExtendedFunctionCode;
229 UCHAR ucReserved;
410 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
411 UCHAR ucReserved; //may expand to return larger Fbdiv later
412 UCHAR ucFbDiv; //return value
413 UCHAR ucPostDiv; //return value
419 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
421 UCHAR ucPostDiv; //return post div to be written to register
464 UCHAR ucRefDiv; //Output Parameter
465 UCHAR ucPostDiv; //Output Parameter
466 UCHAR ucCntlFlag; //Output Parameter
467 UCHAR ucReserved;
496 UCHAR ucRefDiv; //Output Parameter
497 UCHAR ucPostDiv; //Output Parameter
500 UCHAR ucCntlFlag; //Output Flags
501 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
503 UCHAR ucReserved;
517 UCHAR ucDllSpeed; //Output
518 UCHAR ucPostDiv; //Output
520 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
521 UCHAR ucPllCntlFlag; //Output:
523 UCHAR ucBWCntl;
598 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
599 UCHAR ucPadding[3];
608 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
609 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
610 UCHAR ucPadding[2];
618 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
619 UCHAR ucPadding[3];
629 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
630 UCHAR ucMisc; //Valid only when table revision =1.3 and above
648 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
649 UCHAR ucAction; // 0: turn off encoder
664 UCHAR ucConfig;
672 UCHAR ucAction; // =0: turn off encoder
674 UCHAR ucEncoderMode;
680 UCHAR ucLaneNum; // how many lanes to enable
681 UCHAR ucReserved[2];
723 UCHAR ucReserved1:2;
724 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
725 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
726 UCHAR ucReserved:1;
727 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
729 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
730 UCHAR ucReserved:1;
731 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
732 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
733 UCHAR ucReserved1:2;
742 UCHAR ucAction;
743 UCHAR ucEncoderMode;
749 UCHAR ucLaneNum; // how many lanes to enable
750 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
751 UCHAR ucReserved;
790 UCHAR ucReserved1:1;
791 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
792 UCHAR ucReserved:3;
793 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
795 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
796 UCHAR ucReserved:3;
797 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
798 UCHAR ucReserved1:1;
817 UCHAR ucAction;
819 UCHAR ucEncoderMode;
826 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
831 UCHAR ucLaneNum; // how many lanes to enable
832 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
833 UCHAR ucReserved;
843 UCHAR ucReserved1:1;
844 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
845 UCHAR ucReserved:2;
846 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
848 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
849 UCHAR ucReserved:2;
850 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
851 UCHAR ucReserved1:1;
874 UCHAR ucConfig;
876 UCHAR ucAction;
878 UCHAR ucEncoderMode;
885 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
890 UCHAR ucLaneNum; // how many lanes to enable
891 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
892 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
915 UCHAR ucLaneSel;
916 UCHAR ucLaneSet;
927 UCHAR ucConfig;
941 UCHAR ucAction; // =0: turn off encoder
943 UCHAR ucReserved[4];
996 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
999 UCHAR ucReserved:1;
1000 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1001 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1002 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1005 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1006 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1008 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1009 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1010 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1012 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1013 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1014 UCHAR ucReserved:1;
1015 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1056 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1057 UCHAR ucReserved[4];
1063 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1066 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1067 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1068 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1070 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1071 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1073 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1074 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1075 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1077 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1078 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1079 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1095 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1096 UCHAR ucLaneNum;
1097 UCHAR ucReserved[3];
1138 UCHAR ucLaneSel;
1141 UCHAR ucLaneSet;
1144 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1145 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1146 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1148 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1149 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1150 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1159 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1162 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1163 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1164 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1166 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1167 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1169 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1170 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1171 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1173 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1174 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1175 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1192 UCHAR ucConfig;
1194 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1195 UCHAR ucLaneNum;
1196 UCHAR ucReserved[3];
1228 UCHAR ucReservd1:1;
1229 UCHAR ucHPDSel:3;
1230 UCHAR ucPhyClkSrcId:2;
1231 UCHAR ucCoherentMode:1;
1232 UCHAR ucReserved:1;
1234 UCHAR ucReserved:1;
1235 UCHAR ucCoherentMode:1;
1236 UCHAR ucPhyClkSrcId:2;
1237 UCHAR ucHPDSel:3;
1238 UCHAR ucReservd1:1;
1245 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1246 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1247 UCHAR ucLaneNum; // indicate lane number 1-8
1248 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1249 UCHAR ucDigMode; // indicate DIG mode
1252 UCHAR ucConfig;
1254 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1255 UCHAR ucDPLaneSet;
1256 UCHAR ucReserved;
1257 UCHAR ucReserved1;
1338 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1339 UCHAR ucAction; //
1340 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1341 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1342 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1343 UCHAR ucReserved;
1381 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1386 UCHAR aucPadding[3]; // padding to DWORD aligned
1422 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1423 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1437 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1438 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1439 UCHAR ucPadding[2];
1452 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1453 UCHAR ucPadding[3];
1462 UCHAR ucH_Replication; // horizontal replication
1463 UCHAR ucV_Replication; // vertical replication
1464 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1465 UCHAR ucPadding;
1474 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1475 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1476 UCHAR ucPadding[2];
1482 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1483 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1484 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1485 UCHAR ucPadding;
1519 UCHAR ucPostDiv; // post divider
1520 UCHAR ucFracFbDiv; // fractional feedback divider
1521 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1522 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1523 UCHAR ucCRTC; // Which CRTC uses this Ppll
1524 UCHAR ucPadding;
1539 UCHAR ucPostDiv; // post divider
1540 UCHAR ucFracFbDiv; // fractional feedback divider
1541 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1542 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1543 UCHAR ucCRTC; // Which CRTC uses this Ppll
1544 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1586 UCHAR ucPostDiv; // post divider
1587 UCHAR ucFracFbDiv; // fractional feedback divider
1588 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1589 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1592 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1593 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1595 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1605 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1608 UCHAR ucReserved;
1609 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
1614 UCHAR ucPostDiv; // post divider.
1615 UCHAR ucRefDiv; // Reference divider
1616 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1617 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1619 UCHAR ucEncoderMode; // Encoder mode:
1620 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1662 UCHAR ucPostDiv; // post divider.
1663 UCHAR ucRefDiv; // Reference divider
1664 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1665 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1667 UCHAR ucEncoderMode; // Encoder mode:
1668 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1696 UCHAR ucStatus;
1697 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
1698 UCHAR ucReserved[2];
1712 UCHAR ucTransmitterID;
1713 UCHAR ucEncodeMode;
1716 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
1717 UCHAR ucConfig; //if none DVO, not defined yet
1719 UCHAR ucReserved[3];
1728 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
1729 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1730 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
1731 UCHAR ucExtTransmitterID; // external encoder id.
1732 UCHAR ucReserved[2];
1751 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
1752 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
1753 UCHAR ucReserved[2];
1770 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1771 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
1772 UCHAR ucPadding[2];
1805 UCHAR ucSlaveAddr; //Read from which slave
1806 UCHAR ucLineNumber; //Read from which HW assisted line
1827 UCHAR ucData; //PS data1
1828 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
1829 UCHAR ucSlaveAddr; //Write to which slave
1830 UCHAR ucLineNumber; //Write from which HW assisted line
1838 UCHAR ucSlaveAddr; //Write to which slave
1839 UCHAR ucLineNumber; //Write from which HW assisted line
1852 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1853 UCHAR ucPwrBehaviorId;
1859 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1860 UCHAR ucReserved;
1873 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1874 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1875 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1876 UCHAR ucPadding[3];
1883 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1884 UCHAR ucSpreadSpectrumStep; //
1885 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1886 UCHAR ucSpreadSpectrumDelay;
1887 UCHAR ucSpreadSpectrumRange;
1888 UCHAR ucPadding;
1895 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1896 UCHAR ucSpreadSpectrumStep; //
1897 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1898 UCHAR ucSpreadSpectrumDelay;
1899 UCHAR ucSpreadSpectrumRange;
1900 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
1906 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1910 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1931 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1935 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1986 UCHAR ucMisc; // bit0=0: Enable single link
1990 UCHAR ucAction; // 0: turn off encoder
2007 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2008 UCHAR ucAction; // 0: turn off encoder
2010 UCHAR ucTruncate; // bit0=0: Disable truncate
2014 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2018 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2024 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2056 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2057 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2058 UCHAR ucPadding[2];
2098 UCHAR ucDVOConfig;
2099 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2100 UCHAR ucReseved[4];
2172 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2173 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2174 UCHAR ucVoltageIndex; // An index to tell which voltage level
2175 UCHAR ucReserved;
2180 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2181 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2188 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2189 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2221 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2222 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2262 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2263 UCHAR ucAction; // 0: turn off encoder
2334 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2335 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2336 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2337 UCHAR ucHostPortInfo; // Provides host port configuration information
2347 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2348 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2349 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
2350 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2351 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2352 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2353 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2354 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2355 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2356 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2357 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2358 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2450 UCHAR ucASICMaxTemperature;
2451 UCHAR ucPadding[3]; //Don't use them
2466 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2467 UCHAR ucDesign_ID; //Indicate what is the board design
2468 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2484 UCHAR ucASICMaxTemperature;
2485 UCHAR ucMinAllowedBL_Level;
2486 UCHAR ucPadding[2]; //Don't use them
2502 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2503 UCHAR ucDesign_ID; //Indicate what is the board design
2504 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2520 UCHAR ucASICMaxTemperature;
2521 UCHAR ucMinAllowedBL_Level;
2522 UCHAR ucPadding[2]; //Don't use them
2539 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2540 UCHAR ucDesign_ID; //Indicate what is the board design
2541 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2557 UCHAR ucASICMaxTemperature;
2558 UCHAR ucMinAllowedBL_Level;
2577 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2578 UCHAR ucDesign_ID; //Indicate what is the board design
2579 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2596 UCHAR ucReserved1; //Was ucASICMaxTemperature;
2597 UCHAR ucMinAllowedBL_Level;
2617 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2618 UCHAR ucReserved4[3];
2636 UCHAR ucReserved3; //Was ucASICMaxTemperature;
2637 UCHAR ucMinAllowedBL_Level;
2643 UCHAR ucRemoteDisplayConfig;
2644 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
2655 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2656 UCHAR ucReserved9[3];
2684 UCHAR ucNumberOfCyclesInPeriodHi;
2685 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
2699 UCHAR ucMaxNBVoltage;
2700 UCHAR ucMinNBVoltage;
2701 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
2702 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
2703 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
2704 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2705 UCHAR ucMaxNBVoltageHigh;
2706 UCHAR ucMinNBVoltageHigh;
2763 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2764 UCHAR ucUMAChannelNumber;
2765 UCHAR ucDockingPinBit;
2766 UCHAR ucDockingPinPolarity;
2938 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
2939 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
2946 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2947 UCHAR ucUMAChannelNumber;
3114 UCHAR bfHW_Capable:1;
3115 UCHAR bfHW_EngineID:3;
3116 UCHAR bfI2C_LineMux:4;
3118 UCHAR bfI2C_LineMux:4;
3119 UCHAR bfHW_EngineID:3;
3120 UCHAR bfHW_Capable:1;
3127 UCHAR ucAccess;
3145 UCHAR ucClkMaskShift;
3146 UCHAR ucClkEnShift;
3147 UCHAR ucClkY_Shift;
3148 UCHAR ucClkA_Shift;
3149 UCHAR ucDataMaskShift;
3150 UCHAR ucDataEnShift;
3151 UCHAR ucDataY_Shift;
3152 UCHAR ucDataA_Shift;
3153 UCHAR ucReserved1;
3154 UCHAR ucReserved2;
3262 UCHAR ucH_Border; // From DFP EDID
3263 UCHAR ucV_Border;
3264 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3265 UCHAR ucPadding[3];
3282 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3283 UCHAR ucOverscanRight; // right
3284 UCHAR ucOverscanLeft; // left
3285 UCHAR ucOverscanBottom; // bottom
3286 UCHAR ucOverscanTop; // top
3287 UCHAR ucReserved;
3313 UCHAR ucInternalModeNumber;
3314 UCHAR ucRefreshRate;
3330 UCHAR ucHBorder;
3331 UCHAR ucVBorder;
3333 UCHAR ucInternalModeNumber;
3334 UCHAR ucRefreshRate;
3355 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3356 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3357 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3361 UCHAR ucPanelDefaultRefreshRate;
3362 UCHAR ucPanelIdentification;
3363 UCHAR ucSS_Id;
3375 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3376 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3377 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3381 UCHAR ucPanelDefaultRefreshRate;
3382 UCHAR ucPanelIdentification;
3383 UCHAR ucSS_Id;
3386 UCHAR ucLCDPanel_SpecialHandlingCap;
3387 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3388 UCHAR ucReserved[2];
3438 UCHAR ucLCD_Misc; // Reorganized in V13
3444 UCHAR ucPanelDefaultRefreshRate;
3445 UCHAR ucPanelIdentification;
3446 UCHAR ucSS_Id;
3449 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
3454 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3457 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
3458 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
3459 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
3460 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
3462 UCHAR ucOffDelay_in4Ms;
3463 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
3464 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
3465 UCHAR ucReserved1;
3467 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
3468 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
3469 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
3470 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
3473 UCHAR uceDPToLVDSRxId;
3474 UCHAR ucLcdReservd;
3521 UCHAR ucRecordType;
3528 UCHAR ucRecordType;
3529 UCHAR ucRTSValue;
3536 UCHAR ucRecordType;
3546 UCHAR ucRecordType;
3547 UCHAR ucFakeEDIDLength;
3548 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
3553 UCHAR ucRecordType;
3573 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
3574 UCHAR ucSS_Step;
3575 UCHAR ucSS_Delay;
3576 UCHAR ucSS_Id;
3577 UCHAR ucRecommendedRef_Div;
3578 UCHAR ucSS_Range; //it was reserved for V11
3634 UCHAR ucTV_SupportedStandard;
3635 UCHAR ucTV_BootUpDefaultStandard;
3636 UCHAR ucExt_TV_ASIC_ID;
3637 UCHAR ucExt_TV_ASIC_SlaveAddr;
3647 UCHAR ucTV_SupportedStandard;
3648 UCHAR ucTV_BootUpDefaultStandard;
3649 UCHAR ucExt_TV_ASIC_ID;
3650 UCHAR ucExt_TV_ASIC_SlaveAddr;
3656 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
3657 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
3658 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3659 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
3811 UCHAR ucGpioPinBitShift;
3812 UCHAR ucGPIO_ID;
3836 UCHAR ucSettings;
3837 UCHAR ucReserved;
3879 UCHAR ucBitShift;
3880 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
3882 UCHAR ucMiscInfo;
3883 UCHAR uc480i;
3884 UCHAR uc480p;
3885 UCHAR uc720p;
3886 UCHAR uc1080i;
3887 UCHAR ucLetterBoxMode;
3888 UCHAR ucReserved[3];
3889 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
3899 UCHAR ucMiscInfo;
3900 UCHAR uc480i;
3901 UCHAR uc480p;
3902 UCHAR uc720p;
3903 UCHAR uc1080i;
3904 UCHAR ucReserved;
3905 UCHAR ucLetterBoxMode;
3906 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
3959 UCHAR ucNumOfDispPath;
3960 UCHAR ucVersion;
3961 UCHAR ucPadding[2];
3976 UCHAR ucNumberOfObjects;
3977 UCHAR ucPadding[3];
3983 UCHAR ucNumberOfSrc;
3985 UCHAR ucNumberOfDst;
4021 UCHAR ucDP_Lane3_Source:2;
4022 UCHAR ucDP_Lane2_Source:2;
4023 UCHAR ucDP_Lane1_Source:2;
4024 UCHAR ucDP_Lane0_Source:2;
4026 UCHAR ucDP_Lane0_Source:2;
4027 UCHAR ucDP_Lane1_Source:2;
4028 UCHAR ucDP_Lane2_Source:2;
4029 UCHAR ucDP_Lane3_Source:2;
4041 UCHAR ucDVI_CLK_Source:2;
4042 UCHAR ucDVI_DATA0_Source:2;
4043 UCHAR ucDVI_DATA1_Source:2;
4044 UCHAR ucDVI_DATA2_Source:2;
4046 UCHAR ucDVI_DATA2_Source:2;
4047 UCHAR ucDVI_DATA1_Source:2;
4048 UCHAR ucDVI_DATA0_Source:2;
4049 UCHAR ucDVI_CLK_Source:2;
4058 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
4059 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
4062 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
4066 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4080 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
4082 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
4083 UCHAR uc3DStereoPinId; // use for eDP panel
4084 UCHAR ucRemoteDisplayConfig;
4085 UCHAR uceDPToLVDSRxId;
4086 UCHAR Reserved[4]; // for potential expansion
4092 UCHAR ucRecordType; //An emun to indicate the record type
4093 UCHAR ucRecordSize; //The size of the whole record in byte
4126 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
4132 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4133 UCHAR ucPlugged_PinState;
4140 UCHAR ucProtectionFlag;
4141 UCHAR ucReserved;
4154 UCHAR ucNumberOfDevice;
4155 UCHAR ucReserved;
4163 UCHAR ucConfigGPIOID;
4164 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
4165 UCHAR ucFlowinGPIPID;
4166 UCHAR ucExtInGPIPID;
4172 UCHAR ucCTL1GPIO_ID;
4173 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4174 UCHAR ucCTL2GPIO_ID;
4175 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4176 UCHAR ucCTL3GPIO_ID;
4177 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4178 UCHAR ucCTLFPGA_IN_ID;
4179 UCHAR ucPadding[3];
4185 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4186 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
4192 UCHAR ucTMSGPIO_ID;
4193 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4194 UCHAR ucTCKGPIO_ID;
4195 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4196 UCHAR ucTDOGPIO_ID;
4197 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4198 UCHAR ucTDIGPIO_ID;
4199 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4200 UCHAR ucPadding[2];
4207 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
4208 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4214 UCHAR ucFlags; // Future expnadibility
4215 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
4247 UCHAR ucPadding[2];
4281 UCHAR ucFlowCntlGpioId;
4282 UCHAR ucSwapCntlGpioId;
4283 UCHAR ucConnectedDvoBundle;
4284 UCHAR ucPadding;
4296 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
4297 UCHAR ucReserved;
4304 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
4305 UCHAR ucMuxControlPin;
4306 UCHAR ucMuxState[2]; //for alligment purpose
4312 UCHAR ucMuxType;
4313 UCHAR ucMuxControlPin;
4314 UCHAR ucMuxState[2]; //for alligment purpose
4324 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
4352 UCHAR ucNumOfVoltageEntries;
4353 UCHAR ucBytesPerVoltageEntry;
4354 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
4355 UCHAR ucDefaultVoltageEntry;
4356 UCHAR ucVoltageControlI2cLine;
4357 UCHAR ucVoltageControlAddress;
4358 UCHAR ucVoltageControlOffset;
4365 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
4373 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4374 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
4375 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
4376 UCHAR ucReserved;
4377 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
4388 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4389 UCHAR ucReserved[3];
4395 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
4396 UCHAR ucVoltageControlI2cLine;
4397 UCHAR ucVoltageControlAddress;
4398 UCHAR ucVoltageControlOffset;
4400 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
4401 UCHAR ucReserved;
4421 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4422 UCHAR ucSize; //Size of Object
4429 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4430 UCHAR ucSize; //Size of Object
4449 UCHAR ucLeakageId;
4450 UCHAR ucReserved;
4455 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4456 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
4476 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
4477 UCHAR ucVoltageControlI2cLine;
4478 UCHAR ucVoltageControlAddress;
4479 UCHAR ucVoltageControlOffset;
4487 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
4488 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table
4489 UCHAR ucPhaseDelay; // phase delay in unit of micro second
4490 UCHAR ucReserved;
4498 UCHAR ucLeakageCntlId; // default is 0
4499 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
4500 UCHAR ucReserved[2];
4519 UCHAR ucProfileId;
4520 UCHAR ucReserved;
4540 UCHAR ucPwrSrcId; // Power source
4541 UCHAR ucPwrSensorType; // GPIO, I2C or none
4542 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
4543 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
4544 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
4545 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
4546 UCHAR ucPwrSensActiveState; // high active or low active
4547 UCHAR ucReserve[3]; // reserve
4554 UCHAR asPwrbehave[16];
4600 UCHAR ucHtcTmpLmt;
4601 UCHAR ucHtcHystLmt;
4610 UCHAR ucMemoryType;
4611 UCHAR ucUMAChannelNumber;
4634 UCHAR ulBoostVid_2bit;
4635 UCHAR EnableBoost;
4638 UCHAR ucLvdsMisc;
4639 UCHAR ucLVDSReserved;
4773 UCHAR ucHtcTmpLmt;
4774 UCHAR ucHtcHystLmt;
4783 UCHAR ucMemoryType;
4784 UCHAR ucUMAChannelNumber;
4785 UCHAR strVBIOSMsg[40];
4806 UCHAR ulBoostVid_2bit;
4807 UCHAR EnableBoost;
4810 UCHAR ucLvdsMisc;
4811 UCHAR ucLVDSReserved;
4812 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
4813 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
4814 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
4815 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
4816 UCHAR ucLVDSOffToOnDelay_in4Ms;
4817 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
4818 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
4819 UCHAR ucLVDSReserved1;
4825 UCHAR ucNBDPMEnable;
4826 UCHAR ucReserved[3];
4827 UCHAR ucDPMState0VclkFid;
4828 UCHAR ucDPMState0DclkFid;
4829 UCHAR ucDPMState1VclkFid;
4830 UCHAR ucDPMState1DclkFid;
4831 UCHAR ucDPMState2VclkFid;
4832 UCHAR ucDPMState2DclkFid;
4833 UCHAR ucDPMState3VclkFid;
4834 UCHAR ucDPMState3DclkFid;
4988 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
4989 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
4997 UCHAR ucSSChipID; //SS chip being used
4998 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
4999 UCHAR ucNumOfI2CDataRecords; //number of data block
5021 UCHAR ucClockIndication; //Indicate which clock source needs SS
5022 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
5023 UCHAR ucReserved[2];
5045 UCHAR ucClockIndication; //Indicate which clock source needs SS
5046 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5047 UCHAR ucReserved[2];
5076 UCHAR ucClockIndication; //Indicate which clock source needs SS
5077 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5078 UCHAR ucReserved[2];
5542 UCHAR ucAction; //not define yet
5543 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
5544 UCHAR ucFbDiv; //FB value
5545 UCHAR ucPostDiv; //Post div
5556 UCHAR ucGPIO_ID; //return value, read from GPIO pins
5557 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
5558 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
5559 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
5564 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
5565 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
5566 UCHAR ucTVStandard; //
5567 UCHAR ucPadding[1];
5580 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
5581 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
5582 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
5583 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5596 UCHAR ucSurface; // Surface 1 or 2
5597 UCHAR ucPadding[3];
5604 UCHAR ucSurface; // Surface 1 or 2
5605 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5606 UCHAR ucPadding[2];
5613 UCHAR ucSurface; // Surface 1 or 2
5614 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5623 UCHAR ucColorDepth;
5624 UCHAR ucPixelFormat;
5625 UCHAR ucSurface; // Surface 1 or 2
5626 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5627 UCHAR ucModeType;
5628 UCHAR ucReserved;
5668 UCHAR ucLutId;
5669 UCHAR ucAction;
5683 UCHAR ucInterruptId;
5684 UCHAR ucServiceId;
5685 UCHAR ucStatus;
5686 UCHAR ucReserved;
5709 UCHAR IOAccessSequence[256];
5741 UCHAR ucVMode_Num; //Video mode number
5742 UCHAR ucTV_Mode_Num; //Internal TV mode number
5760 UCHAR ucTV_Mode_Num;
5792 UCHAR ucMemoryType;
5793 UCHAR ucMemoryVendor;
5794 UCHAR ucAdjMCId;
5795 UCHAR ucDynClkId;
5825 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
5906 UCHAR ucRevision;
5907 UCHAR ucChecksum;
5908 UCHAR ucReserved1;
5909 UCHAR ucReserved2;
5927 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
5928 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
5929 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
5930 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
5931 UCHAR ucRow; // Number of Row,in power of 2;
5932 UCHAR ucColumn; // Number of Column,in power of 2;
5933 UCHAR ucBank; // Nunber of Bank;
5934 UCHAR ucRank; // Number of Rank, in power of 2
5935 UCHAR ucChannelNum; // Number of channel;
5936 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
5937 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5938 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5939 UCHAR ucReserved[2];
5954 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
5955 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
5956 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
5957 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
5958 UCHAR ucRow; // Number of Row,in power of 2;
5959 UCHAR ucColumn; // Number of Column,in power of 2;
5960 UCHAR ucBank; // Nunber of Bank;
5961 UCHAR ucRank; // Number of Rank, in power of 2
5962 UCHAR ucChannelNum; // Number of channel;
5963 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
5964 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5965 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5966 UCHAR ucRefreshRateFactor;
5967 UCHAR ucReserved[3];
5982 UCHAR ucCL; // CAS latency
5983 UCHAR ucWL; // WRITE Latency
5984 UCHAR uctRAS; // tRAS
5985 UCHAR uctRC; // tRC
5986 UCHAR uctRFC; // tRFC
5987 UCHAR uctRCDR; // tRCDR
5988 UCHAR uctRCDW; // tRCDW
5989 UCHAR uctRP; // tRP
5990 UCHAR uctRRD; // tRRD
5991 UCHAR uctWR; // tWR
5992 UCHAR uctWTR; // tWTR
5993 UCHAR uctPDIX; // tPDIX
5994 UCHAR uctFAW; // tFAW
5995 UCHAR uctAOND; // tAOND
5999 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6000 UCHAR ucReserved;
6012 UCHAR ucCL; // CAS latency
6013 UCHAR ucWL; // WRITE Latency
6014 UCHAR uctRAS; // tRAS
6015 UCHAR uctRC; // tRC
6016 UCHAR uctRFC; // tRFC
6017 UCHAR uctRCDR; // tRCDR
6018 UCHAR uctRCDW; // tRCDW
6019 UCHAR uctRP; // tRP
6020 UCHAR uctRRD; // tRRD
6021 UCHAR uctWR; // tWR
6022 UCHAR uctWTR; // tWTR
6023 UCHAR uctPDIX; // tPDIX
6024 UCHAR uctFAW; // tFAW
6025 UCHAR uctAOND; // tAOND
6026 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6028 UCHAR uctCCDL; //
6029 UCHAR uctCRCRL; //
6030 UCHAR uctCRCWL; //
6031 UCHAR uctCKE; //
6032 UCHAR uctCKRSE; //
6033 UCHAR uctCKRSX; //
6034 UCHAR uctFAW32; //
6035 UCHAR ucMR5lo; //
6036 UCHAR ucMR5hi; //
6037 UCHAR ucTerminator;
6045 UCHAR ucCL; // CAS latency
6046 UCHAR ucWL; // WRITE Latency
6047 UCHAR uctRAS; // tRAS
6048 UCHAR uctRC; // tRC
6049 UCHAR uctRFC; // tRFC
6050 UCHAR uctRCDR; // tRCDR
6051 UCHAR uctRCDW; // tRCDW
6052 UCHAR uctRP; // tRP
6053 UCHAR uctRRD; // tRRD
6054 UCHAR uctWR; // tWR
6055 UCHAR uctWTR; // tWTR
6056 UCHAR uctPDIX; // tPDIX
6057 UCHAR uctFAW; // tFAW
6058 UCHAR uctAOND; // tAOND
6059 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6061 UCHAR uctCCDL; //
6062 UCHAR uctCRCRL; //
6063 UCHAR uctCRCWL; //
6064 UCHAR uctCKE; //
6065 UCHAR uctCKRSE; //
6066 UCHAR uctCKRSX; //
6067 UCHAR uctFAW32; //
6068 UCHAR ucMR4lo; //
6069 UCHAR ucMR4hi; //
6070 UCHAR ucMR5lo; //
6071 UCHAR ucMR5hi; //
6072 UCHAR ucTerminator;
6073 UCHAR ucReserved;
6087 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
6088 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
6089 UCHAR ucRow; // Number of Row,in power of 2;
6090 UCHAR ucColumn; // Number of Column,in power of 2;
6091 UCHAR ucBank; // Nunber of Bank;
6092 UCHAR ucRank; // Number of Rank, in power of 2
6093 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
6094 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
6095 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
6096 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6097 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
6098 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
6109 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6110 UCHAR ucChannelNum; // board dependent parameter:Number of channel;
6111 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
6112 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6113 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6114 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6132 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6133 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6134 UCHAR ucChannelNum; // Number of channels present in this module config
6135 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6136 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6137 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6138 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6139 UCHAR ucVREFI; // board dependent parameter
6140 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6141 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6142 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6144 UCHAR ucReserved[3];
6155 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
6156 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6157 UCHAR ucReserved2[2];
6174 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6175 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6176 UCHAR ucChannelNum; // Number of channels present in this module config
6177 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6178 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6179 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6180 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6181 UCHAR ucVREFI; // board dependent parameter
6182 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6183 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6184 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6186 UCHAR ucReserved[3];
6191 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
6192 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6193 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
6194 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6205 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6206 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6207 UCHAR ucChannelNum; // Number of channels present in this module config
6208 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6209 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6210 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6211 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6212 UCHAR ucVREFI; // board dependent parameter
6213 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6214 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6215 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6217 UCHAR ucReserved[3];
6222 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
6223 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6224 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
6225 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6236 UCHAR ucExtMemoryID; // Current memory module ID
6237 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
6238 UCHAR ucChannelNum; // Number of mem. channels supported in this module
6239 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
6240 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6241 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now.
6242 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
6243 UCHAR ucVREFI; // Not used.
6244 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6245 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6246 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6248 UCHAR ucReserved;
6252 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
6253 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6254 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
6255 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6262 UCHAR ucNumOfVRAMModule;
6272 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
6273 UCHAR ucNumOfVRAMModule;
6287 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
6289 UCHAR ucReservde[4];
6290 UCHAR ucNumOfVRAMModule;
6303 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
6304 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
6305 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
6306 UCHAR ucReserved;
6314 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
6321 UCHAR ucTrainingLoop;
6322 UCHAR ucReserved[3];
6329 UCHAR ucControl;
6330 UCHAR ucData;
6331 UCHAR ucSatus;
6332 UCHAR ucTemp;
6340 UCHAR ucAct;
6341 UCHAR ucData;
6387 UCHAR VbeSignature[4];
6390 UCHAR Capabilities[4];
6414 UCHAR Reserved[222];
6415 UCHAR OemData[256];
6423 UCHAR RedBPP;
6424 UCHAR GreenBPP;
6425 UCHAR BlueBPP;
6426 UCHAR ReservedBPP;
6429 UCHAR Reserved[14];
6436 UCHAR WinAAttributes; // db ? ; window A attributes
6437 UCHAR WinBAttributes; // db ? ; window B attributes
6448 UCHAR XCharSize; // db ? ; character cell width in pixels
6449 UCHAR YCharSize; // db ? ; character cell height in pixels
6450 UCHAR NumberOfPlanes; // db ? ; number of memory planes
6451 UCHAR BitsPerPixel; // db ? ; bits per pixel
6452 UCHAR NumberOfBanks; // db ? ; number of banks
6453 UCHAR MemoryModel; // db ? ; memory model type
6454 UCHAR BankSize; // db ? ; bank size in KB
6455 UCHAR NumberOfImagePages;// db ? ; number of images
6456 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
6459 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
6460 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
6461 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
6462 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
6463 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
6464 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
6465 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
6466 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
6467 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
6476 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
6477 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
6478 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
6479 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
6480 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
6481 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
6482 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
6483 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
6484 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
6485 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
6487 UCHAR Reserved; // db 190 dup (0)
6543 UCHAR ucTransmitterCmdTblId;
6544 UCHAR ucConfig;
6545 UCHAR ucEncoderID; //available 1st encoder ( default )
6546 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
6547 UCHAR uc2ndEncoderID;
6548 UCHAR ucReserved;
6563 UCHAR ucEncoderID;
6564 UCHAR ucEncoderConfig;
6589 UCHAR ucPpllId;
6590 UCHAR ucPpllAttribute;
6603 UCHAR ucTransmitterCmdTblId;
6604 UCHAR ucConfig;
6605 UCHAR ucEncoderID; // available 1st encoder ( default )
6606 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
6607 UCHAR uc2ndEncoderID;
6608 UCHAR ucReserved;
6618 UCHAR ucDCERevision;
6619 UCHAR ucMaxDispEngineNum;
6620 UCHAR ucMaxActiveDispEngineNum;
6621 UCHAR ucMaxPPLLNum;
6622 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
6623 UCHAR ucReserved[3];
6645 UCHAR ucChannelID;
6648 UCHAR ucReplyStatus;
6649 UCHAR ucDelay;
6651 UCHAR ucDataOutLen;
6652 UCHAR ucReserved;
6660 UCHAR ucChannelID;
6663 UCHAR ucReplyStatus;
6664 UCHAR ucDelay;
6666 UCHAR ucDataOutLen;
6667 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
6679 UCHAR ucConfig; // for DP training command
6680 UCHAR ucI2cId; // use for GET_SINK_TYPE command
6682 UCHAR ucAction;
6683 UCHAR ucStatus;
6684 UCHAR ucLaneNum;
6685 UCHAR ucReserved[2];
6713 UCHAR ucAuxId;
6714 UCHAR ucAction;
6715 UCHAR ucSinkType; // Iput and Output parameters.
6716 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
6717 UCHAR ucReserved[2];
6748 UCHAR ucI2CSpeed;
6751 UCHAR ucRegIndex;
6752 UCHAR ucStatus;
6755 UCHAR ucFlag;
6756 UCHAR ucTransBytes;
6757 UCHAR ucSlaveAddr;
6758 UCHAR ucLineNumber;
6773 UCHAR ucCmd; // Input: To tell which action to take
6774 UCHAR ucReserved[3];
6780 UCHAR ucReturnCode; // Output: Return value base on action was taken
6781 UCHAR ucReserved[3];
6803 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
6804 UCHAR ucReserved[3];
6833 UCHAR ucStartBit;
6834 UCHAR ucEndBit;
6839 UCHAR ucEncodeMode;
6840 UCHAR ucPhySel;
6861 UCHAR ucEncodeMode;
6862 UCHAR ucPhySel;
6898 UCHAR ucDAC1_BG_Adjustment;
6899 UCHAR ucDAC1_DAC_Adjustment;
6902 UCHAR ucDAC2_CRT2_BG_Adjustment;
6903 UCHAR ucDAC2_CRT2_DAC_Adjustment;
6906 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6907 UCHAR ucDAC2_NTSC_BG_Adjustment;
6908 UCHAR ucDAC2_NTSC_DAC_Adjustment;
6911 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6912 UCHAR ucDAC2_CV_BG_Adjustment;
6913 UCHAR ucDAC2_CV_DAC_Adjustment;
6916 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6917 UCHAR ucDAC2_PAL_BG_Adjustment;
6918 UCHAR ucDAC2_PAL_DAC_Adjustment;
6949 UCHAR bfConnectorType:4;
6950 UCHAR bfAssociatedDAC:4;
6952 UCHAR bfAssociatedDAC:4;
6953 UCHAR bfConnectorType:4;
6960 UCHAR ucAccess;
6981 UCHAR ucIntSrcBitmap;
7007 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7008 UCHAR ucPLL_DutyCycle; // PLL duty cycle control
7009 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
7010 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
7026 UCHAR ucTVStandard; //Same as TV standards defined above,
7027 UCHAR ucPadding[1];
7032 UCHAR ucAttribute; //Same as other digital encoder attributes defined above
7033 UCHAR ucPadding[1];
7047 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
7048 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
7072 UCHAR ucXtransimitterID;
7073 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
7074 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
7076 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
7077 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
7082 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
7083 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
7084 UCHAR ucPadding[2];
7152 UCHAR ucVoltageDropIndex; // index to GPIO table
7153 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7154 UCHAR ucMinTemperature;
7155 UCHAR ucMaxTemperature;
7156 UCHAR ucNumPciELanes; // number of PCIE lanes
7167 UCHAR ucVoltageDropIndex; // index to GPIO table
7168 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7169 UCHAR ucMinTemperature;
7170 UCHAR ucMaxTemperature;
7171 UCHAR ucNumPciELanes; // number of PCIE lanes
7182 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
7183 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7184 UCHAR ucMinTemperature;
7185 UCHAR ucMaxTemperature;
7186 UCHAR ucNumPciELanes; // number of PCIE lanes
7187 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
7208 UCHAR ucOverdriveThermalController;
7209 UCHAR ucOverdriveI2cLine;
7210 UCHAR ucOverdriveIntBitmap;
7211 UCHAR ucOverdriveControllerAddress;
7212 UCHAR ucSizeOfPowerModeEntry;
7213 UCHAR ucNumOfPowerModeEntries;
7220 UCHAR ucOverdriveThermalController;
7221 UCHAR ucOverdriveI2cLine;
7222 UCHAR ucOverdriveIntBitmap;
7223 UCHAR ucOverdriveControllerAddress;
7224 UCHAR ucSizeOfPowerModeEntry;
7225 UCHAR ucNumOfPowerModeEntries;
7232 UCHAR ucOverdriveThermalController;
7233 UCHAR ucOverdriveI2cLine;
7234 UCHAR ucOverdriveIntBitmap;
7235 UCHAR ucOverdriveControllerAddress;
7236 UCHAR ucSizeOfPowerModeEntry;
7237 UCHAR ucNumOfPowerModeEntries;
7246 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_*
7247 UCHAR ucI2cLine; // as interpreted by DAL I2C
7248 UCHAR ucI2cAddress;
7249 UCHAR ucFanParameters; // Fan Control Parameters.
7250 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only.
7251 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only.
7252 UCHAR ucReserved; // ----
7253 UCHAR ucFlags; // to be defined
7287 UCHAR ucNonClockStateIndex;
7288 UCHAR ucClockStateIndices[1]; // variable-sized
7294 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same.
7295 UCHAR ucTHyst; // Temperature hysteresis. Integer.
7345 UCHAR ucDataRevision;
7347 UCHAR ucNumStates;
7348 UCHAR ucStateEntrySize;
7349 UCHAR ucClockInfoSize;
7350 UCHAR ucNonClockSize;
7378 UCHAR ucNumCustomThermalPolicy;
7482 UCHAR ucMinTemperature;
7483 UCHAR ucMaxTemperature;
7484 UCHAR ucThermalAction;
7495 UCHAR ucMinTemperature;
7496 UCHAR ucMaxTemperature;
7498 UCHAR ucRequiredPower;
7502 UCHAR ucUnused[5];
7511 UCHAR ucEngineClockHigh;
7514 UCHAR ucMemoryClockHigh;
7535 UCHAR ucEngineClockHigh;
7538 UCHAR ucMemoryClockHigh;
7551 UCHAR ucEngineClockHigh;
7554 UCHAR ucMemoryClockHigh;
7558 UCHAR ucPCIEGen;
7559 UCHAR ucUnused1;
7570 UCHAR ucLowEngineClockHigh;
7572 UCHAR ucHighEngineClockHigh;
7574 UCHAR ucMemoryClockHigh; // Currentyl unused.
7575 UCHAR ucPadding; // For proper alignment and size.
7577 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
7578 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement.
7598 UCHAR ucEngineClockHigh; //clockfrequency >> 16.
7599 UCHAR vddcIndex; //2-bit vddc index;
7612 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
7613 UCHAR ucNumDPMLevels;
7616 UCHAR nonClockInfoIndex;
7620 UCHAR clockInfoIndex[1];
7625 UCHAR ucNumEntries;
7633 UCHAR ucNumEntries;
7636 UCHAR ucEntrySize;
7638 UCHAR clockInfo[1];
7644 UCHAR ucNumEntries;
7646 UCHAR ucEntrySize;
7654 UCHAR ucClockHigh;
7660 UCHAR ucNumEntries; // Number of entries.
7667 UCHAR ucSclkHigh;
7669 UCHAR ucMclkHigh;
7676 UCHAR ucNumEntries; // Number of entries.
7688 UCHAR ucNumEntries; // Number of entries.
7696 UCHAR ucSclkHigh;
7698 UCHAR ucMclkHigh;
7703 UCHAR ucNumEntries; // Number of entries.
7709 UCHAR ucEVClkHigh;
7711 UCHAR ucECClkHigh;
7715 UCHAR ucNumEntries;
7722 UCHAR ucVCEClockInfoIndex;
7727 UCHAR numEntries;
7733 UCHAR ucVCEClockInfoIndex;
7734 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
7739 UCHAR numEntries;
7746 UCHAR revid;
7755 UCHAR ucVClkHigh;
7757 UCHAR ucDClkHigh;
7761 UCHAR ucNumEntries;
7768 UCHAR ucUVDClockInfoIndex;
7773 UCHAR numEntries;
7779 UCHAR ucUVDClockInfoIndex;
7780 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
7785 UCHAR numEntries;
7792 UCHAR revid;
7955 UCHAR Revision;
7956 UCHAR Checksum;
7957 UCHAR OemId[6];
7958 UCHAR OemTableId[8]; //UINT64 OemTableId;
7979 UCHAR TableUUID[16]; //0x24
8000 UCHAR VbiosContent[1];
8005 UCHAR Lib1Content[1];