nvidia_gpgpu/engine/nv_acc_dma.c

569 	si->engine.fifo.handle[0] = NV_ROP5_SOLID;
570 	si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;
571 	si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;
572 	si->engine.fifo.handle[3] = NV4_SURFACE; /* NV10_CONTEXT_SURFACES_2D is identical */
573 	si->engine.fifo.handle[4] = NV_IMAGE_BLIT;
574 	si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;
576 	si->engine.fifo.handle[6] = 0;
577 	si->engine.fifo.handle[7] = 0;
581 		si->engine.fifo.ch_ptr[cnt] = 0;
588 		si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =
612 	/* wait for room in fifo for new FIFO assigment cmds if needed: */
617 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]);
619 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]);
621 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]);
623 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]);
625 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]);
627 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);
651 	/* wait for room in fifo for surface setup cmd if needed */
665 	/* wait for room in fifo for pattern colordepth setup cmd if needed */
671 	/* wait for room in fifo for bitmap colordepth setup cmd if needed */
678 	/* wait for room in fifo for pattern cmd if needed. */
842 		((si->engine.fifo.ch_ptr[cmd] + offset) & 0x0000fffc));
860  * switching fifo channel assignments this way has no noticable slowdown:
866 	if (!si->engine.fifo.ch_ptr[NV_ROP5_SOLID] ||
867 		!si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE] ||
868 		!si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN] ||
869 		!si->engine.fifo.ch_ptr[NV4_SURFACE] ||
870 		!si->engine.fifo.ch_ptr[NV_IMAGE_BLIT] ||
871 		!si->engine.fifo.ch_ptr[NV4_GDI_RECTANGLE_TEXT] ||
872 		!si->engine.fifo.ch_ptr[NV_SCALED_IMAGE_FROM_MEMORY])
877 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[0]] = 0;
878 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[1]] = 0;
879 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[2]] = 0;
880 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[3]] = 0;
881 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[4]] = 0;
882 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[5]] = 0;
883 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[6]] = 0;
886 		si->engine.fifo.handle[0] = NV_ROP5_SOLID;
887 		si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;
888 		si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;
889 		si->engine.fifo.handle[3] = NV4_SURFACE;
890 		si->engine.fifo.handle[4] = NV_IMAGE_BLIT;
891 		si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;
892 		si->engine.fifo.handle[6] = NV_SCALED_IMAGE_FROM_MEMORY;
899 			si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =
903 		/* wait for room in fifo for new FIFO assigment cmds if needed. */
908 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]);
910 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]);
912 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]);
914 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]);
916 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]);
918 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);
920 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]);
951 	 * wait for room in fifo for ROP cmd if needed. */
968 		/* wait for room in fifo for blit cmd if needed. */
1042 		/* wait for room in fifo for surface setup cmd if needed */
1050 	/* wait for room in fifo for cmds if needed. */
1071 		/* wait for room in fifo for blit cmd if needed. */
1129 		/* wait for room in fifo for surface setup cmd if needed */
1152 	 * wait for room in fifo for ROP and bitmap cmd if needed. */
1170 		/* wait for room in fifo for bitmap cmd if needed. */
1204 	 * wait for room in fifo for ROP and bitmap cmd if needed. */
1222 		/* wait for room in fifo for bitmap cmd if needed. */
1255 	 * wait for room in fifo for ROP and bitmap cmd if needed. */
1273 		/* wait for room in fifo for bitmap cmd if needed. */