nvidia/engine/nv_acc_dma.c

133 		/* set framebuffer config: type = notiling, PRAMIN write access enabled */
595 		/* setup location of active screen in framebuffer */
596 		ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
597 		ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
651 		/* setup location of active screen in framebuffer */
652 		ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
653 		ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
858 				/* setup location of active screen in framebuffer */
859 				ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
860 				ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
884 				/* setup location of active screen in framebuffer */
885 				ACCW(NV40P_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
886 				ACCW(NV40P_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
907 			/* setup location of active screen in framebuffer */
908 			ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
909 			ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
1052 		si->dma_buffer = (void *)((char *)si->framebuffer +
1138 		((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetSource */
1140 		((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetDest */
1437 			/* dummy read the first adress of the framebuffer to flush MTRR-WC buffers */
1438 			dummy = *((volatile uint32 *)(si->framebuffer));
1856 				((uint32)((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)) +
2016 			(uint32)((uint8*)config->buffer - (uint8*)si->framebuffer +