alpha/ev6/aorsmul_1.asm

0 dnl  Alpha ev6 mpn_addmul_1 and mpn_submul_1.
3 dnl  Copyright 2000, 2003, 2004, 2005, 2008 Free Software Foundation, Inc.
5 dnl  This file is part of the GNU MP Library.
7 dnl  The GNU MP Library is free software; you can redistribute it and/or modify
8 dnl  it under the terms of the GNU Lesser General Public License as published
9 dnl  by the Free Software Foundation; either version 3 of the License, or (at
10 dnl  your option) any later version.
12 dnl  The GNU MP Library is distributed in the hope that it will be useful, but
13 dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
15 dnl  License for more details.
17 dnl  You should have received a copy of the GNU Lesser General Public License
18 dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.
33 dnl  This code was written in cooperation with ev6 pipeline expert Steve Root.
35 dnl  The stores can issue a cycle late so we have paired no-op's to 'catch'
36 dnl  them, so that further disturbance to the schedule is damped.
38 dnl  We couldn't pair the loads, because the entangled schedule of the carry's
39 dnl  has to happen on one side {0} of the machine.
41 dnl  This is a great schedule for the d_cache, a poor schedule for the b_cache.
42 dnl  The lockup on U0 means that any stall can't be recovered from.  Consider a
43 dnl  ldq in L1, say that load gets stalled because it collides with a fill from
44 dnl  the b_cache.  On the next cycle, this load gets priority.  If first looks
45 dnl  at L0, and goes there.  The instruction we intended for L0 gets to look at
46 dnl  L1, which is NOT where we want it.  It either stalls 1, because it can't
47 dnl  go in L0, or goes there, and causes a further instruction to stall.
49 dnl  So for b_cache, we're likely going to want to put one or more cycles back
50 dnl  into the code! And, of course, put in lds prefetch for the rp[] operand.
51 dnl  At a place where we have an mt followed by a bookkeeping, put the
52 dnl  bookkeeping in upper, and the prefetch into lower.
54 dnl  Note, the ldq's and stq's are at the end of the quadpacks.  Note, we'd
55 dnl  like not to have an ldq or an stq to preceded a conditional branch in a
56 dnl  quadpack.  The conditional branch moves the retire pointer one cycle
57 dnl  later.