config/ia64/ia64.c

1418 /* Split a post-reload TImode or TFmode reference into two DImode
1441       out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1442       out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1454 	   quantity into a pair of DImode constants.  */
1489 		  (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1491 		  (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1499 		  (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1500 		out[1] = adjust_address (in, DImode, 0);
1508 	    out[0] = adjust_automodify_address (in, DImode, 0, 0);
1509 	    out[1] = adjust_automodify_address (in, DImode, 0, 8);
1518 	      (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1520 	      (in, DImode,
1538 	      (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1544 		out[1] = adjust_automodify_address (in, DImode, 0, 8);
1556 		    out[1] = adjust_automodify_address (in, DImode, base, 8);
1565 		      (in, DImode, gen_rtx_POST_MODIFY
1698      DImode loads for convenience.  We also need to support XFmode stores
1730 	  emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1733 	  emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1746       out[0] = gen_rtx_REG (DImode, REGNO (op0));
1747       out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1749       emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1750       emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1778 	  in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1779 	  in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1781 	  emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1782 	  emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1879       ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1881 				     GEN_INT (magic), DImode);
2196   addr = convert_memory_address (DImode, addr);
2197   b0 = gen_rtx_REG (DImode, R_BR (0));
2228 	     gen_rtx_REG (DImode, GR_REG (25)));
2265       tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp));
2295       tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2391   if ((mode == SImode || mode == DImode)
2448   old_reg = gen_reg_rtx (DImode);
2449   cmp_reg = gen_reg_rtx (DImode);
2452   if (mode != DImode)
2454       val = simplify_gen_subreg (DImode, val, mode, 0);
2455       emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2462   ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2472       new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX,
2474       new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true);
2477     new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2480   if (mode != DImode)
2496 	case DImode: icode = CODE_FOR_cmpxchg_acq_di;  break;
2512 	case DImode: icode = CODE_FOR_cmpxchg_rel_di;  break;
2524   emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
3103       spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
3127 	    = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
3128 				   gen_rtx_PLUS (DImode,
3139 	      rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3173 	      rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3340 			  gen_rtx_ZERO_EXTRACT (DImode, r3, GEN_INT (12),
3637       ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3650 				     gen_rtx_REG (DImode, AR_PFS_REGNUM)));
3680 	  offset = gen_rtx_REG (DImode, regno);
3693 				     gen_rtx_PLUS (DImode,
3711 	    = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3717 	  ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3721       reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3744       reg = gen_rtx_REG (DImode, regno);
3756       reg = gen_rtx_REG (DImode, PR_REG (0));
3759 	  alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3763 	  /* ??? Denote pr spill/fill by a DImode move that modifies all
3776 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
3787       reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3798       reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3805       reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3808 	  alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3822 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
3832       reg = gen_rtx_REG (DImode, BR_REG (0));
3835           alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3850 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
3860       insn = emit_move_insn (gen_rtx_REG (DImode,
3873 	reg = gen_rtx_REG (DImode, regno);
3883 	alt_reg = gen_rtx_REG (DImode, alt_regno);
3884 	reg = gen_rtx_REG (DImode, regno);
3965 	  alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3971 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
3975       reg = gen_rtx_REG (DImode, PR_REG (0));
3988 	    = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3994 	  ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
4006       alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]);
4007       reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
4013       alt_reg = gen_rtx_REG (DImode, alt_regno);
4016       reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
4024 	  alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
4030 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
4034       reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
4043          alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
4049 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
4053       reg = gen_rtx_REG (DImode, BR_REG (0));
4070 	reg = gen_rtx_REG (DImode, regno);
4080 	alt_reg = gen_rtx_REG (DImode, alt_regno);
4083 	reg = gen_rtx_REG (DImode, regno);
4100       reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
4137 	  offset = gen_rtx_REG (DImode, regno);
4148 				 gen_rtx_PLUS (DImode,
4157     emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
4182 	  insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
4242 	  src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
4282     src = gen_rtx_REG (DImode, BR_REG (0));
4739       emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)),
4806       /* Fill in the GR regs.  We must use DImode here, not the hfa mode.  */
4810 	  machine_mode gr_mode = DImode;
4856 					  gen_rtx_REG (DImode,
4880 		     gen_rtx_REG (DImode, basereg + cum->words + offset),
4891 	(BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
5256 					  gen_rtx_REG (DImode,
5324    e    Print 64 - constant, for DImode rotates.
5555       x = simplify_subreg (DImode, x, GET_MODE (x), 0);
5937       /* This can happen when we take a BImode subreg of a DImode value,
5938 	 and that DImode value winds up in some non-GR register.  */
7968     case DImode: return 4;
8063      ZERO_EXTEND will always be DImode.  */
10526       if (! target || ! register_operand (target, DImode))
10527 	target = gen_reg_rtx (DImode);
10648   set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
10651   set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
10654   set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
10658   set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
10678   set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
10679   set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
10680   set_optab_libfunc (smod_optab, DImode, "__milli_remI");
10681   set_optab_libfunc (umod_optab, DImode, "__milli_remU");
10706   set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10708   set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10710   set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10712   set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10752   return (mode == SImode || mode == DImode);
10994     case DImode:
11415   tmp = gen_reg_rtx (DImode);
11416   hi = gen_lowpart (DImode, hi);
11417   lo = gen_lowpart (DImode, lo);
11506       temp = gen_reg_rtx (DImode);
11507       emit_insn (gen_extzv (temp, gen_lowpart (DImode, d->op0),