Lines Matching defs:UIMM
642 /* The other UIMM field in a EVX form instruction. */
693 /* The 4-bit UIMM field in a VX form instruction. */
768 /* The UIMM field in a VX form instruction. */
769 #define UIMM SIMM + 1
770 #define DCTL UIMM
773 /* The 3-bit UIMM field in a VX form instruction. */
774 #define UIMM3 UIMM + 1
793 /* The other UIMM field in a half word EVX form instruction. */
797 /* The other UIMM field in a word EVX form instruction. */
801 /* The other UIMM field in a double EVX form instruction. */
958 /* The 2-bit UIMM field in a VX form instruction. */
3387 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3392 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3393 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3562 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3563 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3605 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3606 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3621 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3622 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3631 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3632 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},