binutils/opcodes/arc-opc.c

44 /* Insert RB register into a 32-bit opcode.  */
53 /* Insert RB register with checks.  */
1559 #define RB		(RA_CHK + 1)
1561 #define RB_CHK		(RB + 1)
2177 const unsigned char arg_32bit_rarbrc[]	 = { RA, RB, RC };
2178 const unsigned char arg_32bit_zarbrc[]	 = { ZA, RB, RC };
2179 const unsigned char arg_32bit_rbrbrc[]	 = { RB, RBdup, RC };
2180 const unsigned char arg_32bit_rarbu6[]	 = { RA, RB, UIMM6_20 };
2181 const unsigned char arg_32bit_zarbu6[]	 = { ZA, RB, UIMM6_20 };
2182 const unsigned char arg_32bit_rbrbu6[]	 = { RB, RBdup, UIMM6_20 };
2183 const unsigned char arg_32bit_rbrbs12[]	 = { RB, RBdup, SIMM12_20 };
2185 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2187 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2189 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2197 const unsigned char arg_32bit_rbrc[]   = { RB, RC };
2199 const unsigned char arg_32bit_rbu6[]   = { RB, UIMM6_20 };
2201 const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2348 			      { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2351 			     { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2354   { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2356   { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2358   { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2365   { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2367   { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2369   { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2376   { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2378   { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2380   { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2387   { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2389   { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2391   { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2450     { RA, RB, UIMM6_20 }, { C_F }},
2455     { RA, RB, LIMM }, { C_F }},
2466     { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
2472     { RA, BRAKET, RB, LIMM, BRAKETdup },
2484     { RB, SIMM12_20 }, { C_F }},
2489     { RB, LIMM }, { C_F }},
2500     { RA, RB, UIMM6_20 }, { C_F }},
2505     { RA, RB, LIMM }, { C_F }},
2510     | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
2514     | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2520     { RB, UIMM6_20 }, { C_F, C_CC }},
2525     { RB, LIMM }, { C_F, C_CC }},
2531     { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
2536     { RB, RBdup, LIMM }, { C_F, C_CC }}