Lines Matching refs:dwc

14 #define EP0_LOCK(dwc)   (&(dwc)->eps[EP0_OUT].lock)
16 static void dwc3_queue_setup_locked(dwc3_t* dwc) {
17 io_buffer_cache_flush_invalidate(&dwc->ep0_buffer, 0, sizeof(usb_setup_t));
18 dwc3_ep_start_transfer(dwc, EP0_OUT, TRB_TRBCTL_SETUP, io_buffer_phys(&dwc->ep0_buffer),
20 dwc->ep0_state = EP0_STATE_SETUP;
23 zx_status_t dwc3_ep0_init(dwc3_t* dwc) {
25 zx_status_t status = dwc3_ep_fifo_init(dwc, EP0_OUT);
31 dwc3_endpoint_t* ep = &dwc->eps[i];
41 void dwc3_ep0_reset(dwc3_t* dwc) {
42 mtx_lock(EP0_LOCK(dwc));
43 dwc3_cmd_ep_end_transfer(dwc, EP0_OUT);
44 dwc->ep0_state = EP0_STATE_NONE;
45 mtx_unlock(EP0_LOCK(dwc));
48 void dwc3_ep0_start(dwc3_t* dwc) {
49 mtx_lock(EP0_LOCK(dwc));
50 dwc3_cmd_start_new_config(dwc, EP0_OUT, 0);
51 dwc3_ep_set_config(dwc, EP0_OUT, true);
52 dwc3_ep_set_config(dwc, EP0_IN, true);
54 dwc3_queue_setup_locked(dwc);
55 mtx_unlock(EP0_LOCK(dwc));
58 static zx_status_t dwc3_handle_setup(dwc3_t* dwc, usb_setup_t* setup, void* buffer, size_t length,
67 dwc3_set_address(dwc, setup->wValue);
72 dwc3_reset_configuration(dwc);
73 dwc->configured = false;
74 status = usb_dci_control(&dwc->dci_intf, setup, buffer, length, out_actual);
76 dwc->configured = true;
77 dwc3_start_eps(dwc);
87 dwc3_reset_configuration(dwc);
88 dwc->configured = false;
89 status = usb_dci_control(&dwc->dci_intf, setup, buffer, length, out_actual);
91 dwc->configured = true;
92 dwc3_start_eps(dwc);
97 return usb_dci_control(&dwc->dci_intf, setup, buffer, length, out_actual);
100 void dwc3_ep0_xfer_not_ready(dwc3_t* dwc, unsigned ep_num, unsigned stage) {
101 mtx_lock(EP0_LOCK(dwc));
103 switch (dwc->ep0_state) {
108 dwc3_cmd_ep_set_stall(dwc, EP0_OUT);
109 dwc3_queue_setup_locked(dwc);
115 dwc3_cmd_ep_end_transfer(dwc, EP0_OUT);
116 dwc3_cmd_ep_set_stall(dwc, EP0_OUT);
117 dwc3_queue_setup_locked(dwc);
123 dwc3_cmd_ep_end_transfer(dwc, EP0_IN);
124 dwc3_cmd_ep_set_stall(dwc, EP0_OUT);
125 dwc3_queue_setup_locked(dwc);
130 if (dwc->cur_setup.wLength > 0) {
131 dwc3_ep_start_transfer(dwc, EP0_OUT, TRB_TRBCTL_STATUS_3, 0, 0, false);
133 dwc3_ep_start_transfer(dwc, EP0_OUT, TRB_TRBCTL_STATUS_2, 0, 0, false);
135 dwc->ep0_state = EP0_STATE_STATUS;
140 if (dwc->cur_setup.wLength > 0) {
141 dwc3_ep_start_transfer(dwc, EP0_IN, TRB_TRBCTL_STATUS_3, 0, 0, false);
143 dwc3_ep_start_transfer(dwc, EP0_IN, TRB_TRBCTL_STATUS_2, 0, 0, false);
145 dwc->ep0_state = EP0_STATE_STATUS;
149 zxlogf(ERROR, "dwc3_ep0_xfer_not_ready unhandled state %u\n", dwc->ep0_state);
153 mtx_unlock(EP0_LOCK(dwc));
156 void dwc3_ep0_xfer_complete(dwc3_t* dwc, unsigned ep_num) {
157 mtx_lock(EP0_LOCK(dwc));
159 switch (dwc->ep0_state) {
161 usb_setup_t* setup = &dwc->cur_setup;
163 void* vaddr = io_buffer_virt(&dwc->ep0_buffer);
164 zx_paddr_t paddr = io_buffer_phys(&dwc->ep0_buffer);
174 dwc3_ep_start_transfer(dwc, EP0_OUT, TRB_TRBCTL_CONTROL_DATA, paddr, setup->wLength,
176 dwc->ep0_state = EP0_STATE_DATA_OUT;
179 zx_status_t status = dwc3_handle_setup(dwc, setup, vaddr, dwc->ep0_buffer.size,
183 dwc3_cmd_ep_set_stall(dwc, EP0_OUT);
184 dwc3_queue_setup_locked(dwc);
190 io_buffer_cache_flush(&dwc->ep0_buffer, 0, actual);
191 dwc3_ep_start_transfer(dwc, EP0_IN, TRB_TRBCTL_CONTROL_DATA, paddr, actual, false);
192 dwc->ep0_state = EP0_STATE_DATA_IN;
194 dwc->ep0_state = EP0_STATE_WAIT_NRDY_IN;
200 dwc->ep0_state = EP0_STATE_WAIT_NRDY_IN;
203 dwc->ep0_state = EP0_STATE_WAIT_NRDY_OUT;
206 dwc3_queue_setup_locked(dwc);
212 mtx_unlock(EP0_LOCK(dwc));