lib/amlogic/s905d2-hiu.c

32 static zx_status_t s905d2_pll_init_regs(aml_pll_dev_t* pll_dev) {
33     aml_hiu_dev_t* device = pll_dev->hiu;
35     if (pll_dev->pll_num == HIFI_PLL) {
45     } else if (pll_dev->pll_num == SYS_PLL) {
55     } else if (pll_dev->pll_num == GP0_PLL) {
69 zx_status_t s905d2_pll_init(aml_hiu_dev_t* device, aml_pll_dev_t* pll_dev, hhi_plls_t pll_num) {
71     ZX_DEBUG_ASSERT(pll_dev);
73     pll_dev->hiu = device;
75     pll_dev->rate_table = s905d2_pll_get_rate_table(pll_num);
76     pll_dev->rate_idx = 0;
77     pll_dev->frequency = 0;
78     pll_dev->pll_num = pll_num;
79     pll_dev->rate_count = s905d2_get_rate_table_count(pll_num);
81     ZX_DEBUG_ASSERT(pll_dev->rate_table);
82     ZX_DEBUG_ASSERT(pll_dev->rate_count);
85     s905d2_pll_disable(pll_dev);
87     return s905d2_pll_init_regs(pll_dev);
90 bool s905d2_pll_disable(aml_pll_dev_t* pll_dev) {
91     uint32_t offs = hiu_get_pll_offs(pll_dev);
92     uint32_t ctl0 = hiu_clk_get_reg(pll_dev->hiu, offs);
97     hiu_clk_set_reg(pll_dev->hiu, offs, ctl0);
102 zx_status_t s905d2_pll_ena(aml_pll_dev_t* pll_dev) {
103     ZX_DEBUG_ASSERT(pll_dev);
105     uint32_t offs = hiu_get_pll_offs(pll_dev);
106     uint32_t reg_val = hiu_clk_get_reg(pll_dev->hiu, offs);
110     hiu_clk_set_reg(pll_dev->hiu, offs, reg_val);
115     hiu_clk_set_reg(pll_dev->hiu, offs, reg_val);
119         if (hiu_clk_get_reg(pll_dev->hiu, offs) & HHI_PLL_LOCK) {
134 zx_status_t s905d2_pll_set_rate(aml_pll_dev_t* pll_dev, uint64_t freq) {
135     ZX_DEBUG_ASSERT(pll_dev);
139     zx_status_t status = s905d2_pll_fetch_rate(pll_dev, freq, &pll_rate);
144     bool ena = s905d2_pll_disable(pll_dev);
147     s905d2_pll_init_regs(pll_dev);
149     uint32_t offs = hiu_get_pll_offs(pll_dev);
150     uint32_t ctl0 = hiu_clk_get_reg(pll_dev->hiu, offs);
161     hiu_clk_set_reg(pll_dev->hiu, offs, ctl0);
163     hiu_clk_set_reg(pll_dev->hiu, offs + 4, pll_rate->frac);
166         return s905d2_pll_ena(pll_dev);