gpu/aml-gpu/aml-gpu.c

36     aml_gpu_block_t* gpu_block = gpu->gpu_block;
37     GPU_INFO("Setting clock source to %d: %d\n", clk_source, gpu_block->gpu_clk_freq[clk_source]);
38     uint32_t current_clk_cntl = READ32_HIU_REG(gpu_block->hhi_clock_cntl_offset);
47                                             gpu_block->gpu_clk_freq[clk_source], 1)
51     WRITE32_HIU_REG(gpu_block->hhi_clock_cntl_offset, current_clk_cntl);
58     WRITE32_HIU_REG(gpu_block->hhi_clock_cntl_offset, current_clk_cntl);
64     aml_gpu_block_t* gpu_block = gpu->gpu_block;
65     uint32_t current_clk_cntl = READ32_HIU_REG(gpu_block->hhi_clock_cntl_offset);
72         GPU_INFO("Setting initial clock source to %d: %d\n", clk_source, gpu_block->gpu_clk_freq[clk_source]);
78                                                 gpu_block->gpu_clk_freq[clk_source], 1)
82         WRITE32_HIU_REG(gpu_block->hhi_clock_cntl_offset, current_clk_cntl);
90     aml_gpu_block_t* gpu_block = gpu->gpu_block;
92     temp = READ32_PRESET_REG(gpu_block->reset0_mask_offset);
94     WRITE32_PRESET_REG(gpu_block->reset0_mask_offset, temp);
96     temp = READ32_PRESET_REG(gpu_block->reset0_level_offset);
98     WRITE32_PRESET_REG(gpu_block->reset0_level_offset, temp);
100     temp = READ32_PRESET_REG(gpu_block->reset2_mask_offset);
102     WRITE32_PRESET_REG(gpu_block->reset2_mask_offset, temp);
104     temp = READ32_PRESET_REG(gpu_block->reset2_level_offset);
106     WRITE32_PRESET_REG(gpu_block->reset2_level_offset, temp);
114     temp = READ32_PRESET_REG(gpu_block->reset0_level_offset);
116     WRITE32_PRESET_REG(gpu_block->reset0_level_offset, temp);
118     temp = READ32_PRESET_REG(gpu_block->reset2_level_offset);
120     WRITE32_PRESET_REG(gpu_block->reset2_level_offset, temp);
226         gpu->gpu_block = &s912_gpu_blocks;
229         gpu->gpu_block = &s905d2_gpu_blocks;