display/intel-i915/intel-i915.cpp

33 #include "registers.h"
34 #include "registers-ddi.h"
35 #include "registers-dpll.h"
36 #include "registers-pipe.h"
37 #include "registers-transcoder.h"
38 #include "registers.h"
213 void Controller::HandleHotplug(registers::Ddi ddi, bool long_pulse) {
254 void Controller::HandlePipeVsync(registers::Pipe pipe, zx_time_t timestamp) {
268         registers::PipeRegs regs(pipe);
302     auto nde_rstwrn_opt = registers::NorthDERestetWarning::Get().ReadFrom(mmio_space_.get());
307     if (!WAIT_ON_US(registers::FuseStatus::Get().ReadFrom(mmio_space_.get()).pg0_dist_status(), 5)) {
320     auto dpll_enable = registers::DpllEnable::Get(registers::DPLL_0).ReadFrom(mmio_space_.get());
323         auto cd_clk = registers::CdClockCtl::Get().ReadFrom(mmio_space_.get());
329         auto dpll_ctl1 = registers::DpllControl1::Get().ReadFrom(mmio_space_.get());
330         dpll_ctl1.dpll_link_rate(registers::DPLL_0).set(dpll_ctl1.kLinkRate810Mhz);
331         dpll_ctl1.dpll_override(registers::DPLL_0).set(1);
332         dpll_ctl1.dpll_hdmi_mode(registers::DPLL_0).set(0);
333         dpll_ctl1.dpll_ssc_enable(registers::DPLL_0).set(0);
339         if (!WAIT_ON_MS(registers::Lcpll1Control::Get().ReadFrom(mmio_space_.get()).pll_lock(), 5)) {
380     auto dbuf_ctl = registers::DbufCtl::Get().ReadFrom(mmio_space_.get());
384     if (!WAIT_ON_US(registers::DbufCtl::Get().ReadFrom(mmio_space_.get()).power_state(), 10)) {
405         auto vga_ctl = registers::VgaCtl::Get().ReadFrom(mmio_space());
410     for (unsigned i = 0; i < registers::kPipeCount; i++) {
411         ResetPipe(registers::kPipes[i]);
413         registers::PipeRegs pipe_regs(registers::kPipes[i]);
419         if (i != registers::PIPE_C) {
431         for (unsigned plane_num = 0; plane_num < registers::kImagePlaneCount; plane_num++) {
442 void Controller::ResetPipe(registers::Pipe pipe) {
443     registers::PipeRegs pipe_regs(pipe);
457     for (unsigned plane_num = 0; plane_num < registers::kImagePlaneCount; plane_num++) {
458         plane_buffers_[pipe][plane_num].start = registers::PlaneBufCfg::kBufferCount;
462 bool Controller::ResetTrans(registers::Trans trans) {
463     registers::TranscoderRegs trans_regs(trans);
480     if (trans != registers::TRANS_EDP) {
489 bool Controller::ResetDdi(registers::Ddi ddi) {
490     registers::DdiRegs ddi_regs(ddi);
509     auto pwc2 = registers::PowerWellControl2::Get().ReadFrom(mmio_space());
514     auto dpll_ctrl2 = registers::DpllControl2::Get().ReadFrom(mmio_space());
519         registers::Dpll dpll = static_cast<registers::Dpll>(dpll_ctrl2.ddi_clock_select(ddi).get());
524         if (dplls_[dpll].use_count == 0 && dpll != registers::DPLL_0) {
525             auto dpll_enable = registers::DpllEnable::Get(dpll).ReadFrom(mmio_space());
534 registers::Dpll Controller::SelectDpll(bool is_edp, const dpll_state_t& state) {
535     registers::Dpll res = registers::DPLL_INVALID;
539             res = registers::DPLL_0;
542         for (unsigned i = registers::kDpllCount - 1; i > 0; i--) {
544                 res = static_cast<registers::Dpll>(i);
546                 res = static_cast<registers::Dpll>(i);
552     if (res != registers::DPLL_INVALID) {
563 const dpll_state_t* Controller::GetDpllState(registers::Dpll dpll) {
570 fbl::unique_ptr<DisplayDevice> Controller::QueryDisplay(registers::Ddi ddi) {
590 bool Controller::LoadHardwareState(registers::Ddi ddi, DisplayDevice* device) {
591     registers::DdiRegs regs(ddi);
593     if (!registers::PowerWellControl2::Get().ReadFrom(mmio_space()).ddi_io_power_state(ddi).get()
598     auto pipe = registers::PIPE_INVALID;
599     if (ddi == registers::DDI_A) {
600         registers::TranscoderRegs regs(registers::TRANS_EDP);
604             pipe = registers::PIPE_A;
606             pipe = registers::PIPE_B;
608             pipe = registers::PIPE_C;
611         for (unsigned j = 0; j < registers::kPipeCount; j++) {
612             auto transcoder = registers::kTrans[j];
613             registers::TranscoderRegs regs(transcoder);
616                 pipe = registers::kPipes[j];
622     if (pipe == registers::PIPE_INVALID) {
626     auto dpll_ctrl2 = registers::DpllControl2::Get().ReadFrom(mmio_space());
631     auto dpll = static_cast<registers::Dpll>(dpll_ctrl2.ddi_clock_select(ddi).get());
632     auto dpll_enable = registers::DpllEnable::Get(dpll).ReadFrom(mmio_space());
637     auto dpll_ctrl1 = registers::DpllControl1::Get().ReadFrom(mmio_space());
641         auto dpll_cfg1 = registers::DpllConfig1::Get(dpll).ReadFrom(mmio_space());
642         auto dpll_cfg2 = registers::DpllConfig2::Get(dpll).ReadFrom(mmio_space());
668     for (uint32_t i = 0; i < registers::kDdiCount; i++) {
669         auto disp_device = QueryDisplay(registers::kDdis[i]);
679     for (unsigned i = 0; i < registers::kDpllCount; i++) {
685     bool ddi_needs_reset[registers::kDdiCount] = {};
686     DisplayDevice* device_needs_init[registers::kDdiCount] = {};
687     for (unsigned i = 0; i < registers::kDdiCount; i++) {
688         auto ddi = registers::kDdis[i];
710     for (unsigned i = 0; i < registers::kTransCount; i++) {
711         auto transcoder = registers::kTrans[i];
712         auto pipe = registers::PIPE_INVALID;
720         if (pipe == registers::PIPE_INVALID) {
727     for (unsigned i = 0; i < registers::kDdiCount; i++) {
731         ResetDdi(static_cast<registers::Ddi>(i));
790         DisplayDevice* added_displays[registers::kDdiCount];
822         align = registers::PlaneSurface::kLinearAlignment;
824         align = registers::PlaneSurface::kXTilingAlignment;
826         align = registers::PlaneSurface::kYTilingAlignment;
874 bool Controller::GetPlaneLayer(registers::Pipe pipe, uint32_t plane,
896                 if (plane != registers::kCursorPlane) {
913     ZX_ASSERT(display_count < registers::kPipeCount);
914     return static_cast<uint16_t>(registers::PlaneBufCfg::kBufferCount / display_count);
919                                              uint16_t min_allocs[registers::kPipeCount]
920                                                                 [registers::kImagePlaneCount]) {
924     for (unsigned pipe_num = 0; pipe_num < registers::kPipeCount; pipe_num++) {
925         registers::Pipe pipe = registers::kPipes[pipe_num];
928         for (unsigned plane_num = 0; plane_num < registers::kImagePlaneCount; plane_num++) {
978 void Controller::UpdateAllocations(const uint16_t min_allocs[registers::kPipeCount]
979                                                             [registers::kImagePlaneCount],
980                                    const uint64_t data_rate[registers::kPipeCount]
981                                                            [registers::kImagePlaneCount]) {
982     uint16_t allocs[registers::kPipeCount][registers::kImagePlaneCount];
984     for (unsigned pipe_num = 0; pipe_num < registers::kPipeCount; pipe_num++) {
986         for (unsigned plane_num = 0; plane_num < registers::kImagePlaneCount; plane_num++) {
990             for (unsigned plane_num = 0; plane_num < registers::kImagePlaneCount; plane_num++) {
1000         bool forced_alloc[registers::kImagePlaneCount] = {};
1003             for (unsigned plane_num = 0; plane_num < registers::kImagePlaneCount; plane_num++) {
1016             for (unsigned plane_num = 0; plane_num < registers::kImagePlaneCount; plane_num++) {
1029     for (unsigned pipe_num = 0; pipe_num < registers::kPipeCount; pipe_num++) {
1031         for (unsigned plane_num = 0; plane_num < registers::kImagePlaneCount; plane_num++) {
1035                 cur->start = registers::PlaneBufCfg::kBufferCount;
1043             registers::Pipe pipe = registers::kPipes[pipe_num];
1044             registers::PipeRegs pipe_regs(pipe);
1055             wm0.set_enable(cur->start != registers::PlaneBufCfg::kBufferCount);
1061             if (plane_num == registers::kCursorPlane) {
1068                 wm0.set_enable(cur->start != registers::PlaneBufCfg::kBufferCount);
1083     uint16_t min_allocs[registers::kPipeCount][registers::kImagePlaneCount];
1090     uint64_t data_rate[registers::kPipeCount][registers::kImagePlaneCount];
1091     for (unsigned pipe_num = 0; pipe_num < registers::kPipeCount; pipe_num++) {
1092         registers::Pipe pipe = registers::kPipes[pipe_num];
1093         for (unsigned plane_num = 0; plane_num < registers::kImagePlaneCount; plane_num++) {
1121     buffer_allocation_t active_allocation[registers::kPipeCount];
1129         for (unsigned pipe_num = 0; pipe_num < registers::kPipeCount; pipe_num++) {
1153         buffer_allocation_t active_allocation[registers::kPipeCount]) {
1166         for (unsigned pipe_num = 0; pipe_num < registers::kPipeCount; pipe_num++) {
1178                 for (unsigned other_pipe = 0; other_pipe < registers::kPipeCount; other_pipe++) {
1201                 registers::PipeRegs pipe_regs(registers::kPipes[pipe_num]);
1202                 for (unsigned j = 0; j < registers::kImagePlaneCount; j++) {
1243         auto cd_freq = registers::CdClockCtl::Get().ReadFrom(mmio_space()).cd_freq_decimal();
1244         if (cd_freq == registers::CdClockCtl::kFreqDecimal30857) {
1246         } else if (cd_freq == registers::CdClockCtl::kFreqDecimal3375) {
1248         } else if (cd_freq == registers::CdClockCtl::kFreqDecimal432) {
1250         } else if (cd_freq == registers::CdClockCtl::kFreqDecimal450) {
1252         } else if (cd_freq == registers::CdClockCtl::kFreqDecimal540) {
1254         } else if (cd_freq == registers::CdClockCtl::kFreqDecimal61714) {
1256         } else if (cd_freq == registers::CdClockCtl::kFreqDecimal675) {
1321     uint64_t pipe_alloc[registers::kPipeCount];
1402                     float ratio = registers::PipeScalerCtrl::k7x5MaxRatio;
1411                         float ratio = registers::PipeScalerCtrl::kDynamicMaxVerticalRatio2049;
1422                     bool using_c = pipe_alloc[registers::PIPE_C] == display->id();
1424                             (using_c ? registers::PipeScalerCtrl::kPipeCScalersAvailable
1425                                 : registers::PipeScalerCtrl::kPipeABScalersAvailable)
1426                             || src_width > registers::PipeScalerCtrl::kMaxSrcWidthPx
1427                             || src_width < registers::PipeScalerCtrl::kMinSrcSizePx
1428                             || src_height < registers::PipeScalerCtrl::kMinSrcSizePx
1483     uint16_t arr[registers::kPipeCount][registers::kImagePlaneCount];
1487         for (unsigned pipe_num = 0; pipe_num < registers::kPipeCount; pipe_num++) {
1509                                          uint64_t alloc[registers::kPipeCount]) {
1510     if (display_count > registers::kPipeCount) {
1513     memset(alloc, 0, sizeof(uint64_t) * registers::kPipeCount);
1525             for (unsigned pipe_num = 0; pipe_num < registers::kPipeCount; pipe_num++) {
1543     uint64_t pipe_alloc[registers::kPipeCount];
1560                 for (unsigned i = 0; i < registers::kPipeCount; i++) {
1579     uint64_t fake_vsyncs[registers::kDdiCount];
1750     return registers::kDdiCount * 2;
1774     if (bus_id < registers::kDdiCount) {
1776     } else if (bus_id < 2 * registers::kDdiCount) {
1777         bus_id -= registers::kDdiCount;
1784 bool Controller::DpcdRead(registers::Ddi ddi, uint32_t addr, uint8_t* buf, size_t size) {
1788 bool Controller::DpcdWrite(registers::Ddi ddi, uint32_t addr, const uint8_t* buf, size_t size) {
1836         auto bdsm_reg = registers::BaseDsm::Get().FromValue(0);
1871                 registers::PipeRegs pipe_regs(display->pipe()->pipe());
1890     registers::PanelPowerDivisor::Get().FromValue(pp_divisor_val_).WriteTo(mmio_space_.get());
1891     registers::PanelPowerOffDelay::Get().FromValue(pp_off_delay_val_).WriteTo(mmio_space_.get());
1892     registers::PanelPowerOnDelay::Get().FromValue(pp_on_delay_val_).WriteTo(mmio_space_.get());
1893     registers::SouthBacklightCtl1::Get().FromValue(0)
1895     registers::SouthBacklightCtl2::Get().FromValue(sblc_ctrl2_val_).WriteTo(mmio_space_.get());
1896     registers::SChicken1::Get().FromValue(schicken1_val_).WriteTo(mmio_space_.get());
1898     registers::DdiRegs(registers::DDI_A).DdiBufControl().ReadFrom(mmio_space_.get())
1928             DisplayDevice* added_displays[registers::kDdiCount];
1966     LOG_TRACE("Mapping registers\n");
1984     for (unsigned i = 0; i < registers::kDdiCount; i++) {
1989     pp_divisor_val_ = registers::PanelPowerDivisor::Get().ReadFrom(mmio_space_.get()).reg_value();
1991             registers::PanelPowerOffDelay::Get().ReadFrom(mmio_space_.get()).reg_value();
1992     pp_on_delay_val_  = registers::PanelPowerOnDelay::Get().ReadFrom(mmio_space_.get()).reg_value();
1993     sblc_ctrl2_val_ = registers::SouthBacklightCtl2::Get().ReadFrom(mmio_space_.get()).reg_value();
1994     schicken1_val_ = registers::SChicken1::Get().ReadFrom(mmio_space_.get()).reg_value();
1996     sblc_polarity_ = registers::SouthBacklightCtl1::Get().ReadFrom(mmio_space_.get()).polarity();
1997     ddi_a_lane_capability_control_ = registers::DdiRegs(registers::DDI_A).DdiBufControl()
2074         for (unsigned i = 0; i < registers::kPipeCount; i++) {