display/intel-i915/dp-display.cpp

15 #include "registers.h"
16 #include "registers-ddi.h"
17 #include "registers-dpll.h"
18 #include "registers-pipe.h"
19 #include "registers-transcoder.h"
260     registers::DdiRegs ddi_regs(ddi_);
265         // For some reason intel made these data registers big endian...
307                 // For some reason intel made these data registers big endian...
489 DpAux::DpAux(registers::Ddi ddi) : ddi_(ddi) {
507     // registers with a single operation: "The AUX CH burst write must be
594     registers::DdiRegs ddi_regs(ddi());
603     registers::DdiRegs ddi_regs(ddi());
639     auto disio_cr_tx_bmu = registers::DisplayIoCtrlRegTxBmu::Get().ReadFrom(mmio_space());
642     if (ddi() == registers::DDI_A && dp_lane_count_ == 4) {
643         disio_cr_tx_bmu.tx_balance_leg_select(registers::DDI_E).set(i_boost_val);
751     registers::DdiRegs ddi_regs(ddi());
854 // Convert ratio x/y into the form used by the Link/Data M/N ratio registers.
866 static registers::Trans select_trans(registers::Ddi ddi, registers::Pipe pipe) {
867     if (ddi == registers::DDI_A) {
868         return registers::TRANS_EDP;
870         return static_cast<registers::Trans>(pipe);
878 DpDisplay::DpDisplay(Controller* controller, uint64_t id, registers::Ddi ddi)
941     if ((ddi() == registers::DDI_A || ddi() == registers::DDI_E) && dp_lane_count_ == 4
942             && !registers::DdiRegs(registers::DDI_A).DdiBufControl().ReadFrom(mmio_space())
998         auto panel_ctrl = registers::PanelPowerCtrl::Get().ReadFrom(mmio_space());
999         auto panel_status = registers::PanelPowerStatus::Get().ReadFrom(mmio_space());
1046         dpll_link_rate = registers::DpllControl1::kLinkRate810Mhz;
1048         dpll_link_rate = registers::DpllControl1::kLinkRate1350Mhz;
1051         dpll_link_rate = registers::DpllControl1::kLinkRate2700Mhz;
1054     registers::Dpll dpll = controller()->SelectDpll(is_edp, state);
1055     if (dpll == registers::DPLL_INVALID) {
1059     auto dpll_enable = registers::DpllEnable::Get(dpll).ReadFrom(mmio_space());
1062         auto dpll_ctrl1 = registers::DpllControl1::Get().ReadFrom(mmio_space());
1073         if (!WAIT_ON_MS(registers::DpllStatus
1081     auto dpll_ctrl2 = registers::DpllControl2::Get().ReadFrom(mmio_space());
1088     auto power_well = registers::PowerWellControl2::Get().ReadFrom(mmio_space());
1091     if (!WAIT_ON_US(registers::PowerWellControl2
1109         config->dp_rate = registers::DpllControl1::kLinkRate810Mhz;
1111         config->dp_rate = registers::DpllControl1::kLinkRate1350Mhz;
1114         config->dp_rate = registers::DpllControl1::kLinkRate2700Mhz;
1120                            registers::Pipe pipe, registers::Trans trans) {
1125                                    registers::Pipe pipe, registers::Trans trans) {
1126     registers::TranscoderRegs trans_regs(trans);
1129     if (trans != registers::TRANS_EDP) {
1181                                    registers::Pipe pipe, registers::Trans trans) {
1182     registers::TranscoderRegs trans_regs(trans);
1198     ddi_func.set_edp_input_select(pipe == registers::PIPE_A ? ddi_func.kPipeA :
1199             (pipe == registers::PIPE_B ? ddi_func.kPipeB : ddi_func.kPipeC));
1236         registers::PanelPowerCtrl::Get().ReadFrom(mmio_space())
1238         registers::SouthBacklightCtl1::Get().ReadFrom(mmio_space())
1261         return registers::PanelPowerCtrl::Get().ReadFrom(mmio_space())
1263             || registers::SouthBacklightCtl1::Get().ReadFrom(mmio_space())
1287         auto backlight_ctrl = registers::SouthBacklightCtl2::Get().ReadFrom(mmio_space());
1320                 registers::SouthBacklightCtl2::Get().ReadFrom(mmio_space());
1391 uint32_t DpDisplay::LoadClockRateForTranscoder(registers::Trans transcoder) {
1392     registers::TranscoderRegs trans_regs(transcoder);